Invention Publication
- Patent Title: POWER SEMICONDUCTOR DEVICE WITH REDUCED STRAIN
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Application No.: US18504344Application Date: 2023-11-08
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Publication No.: US20240072131A1Publication Date: 2024-02-29
- Inventor: Daniel Jenner Lichtenwalner , Edward Robert Van Brunt , Thomas E. Harrington, III , Shadi Sabri , Brett Hull , Brice McPherson , Joe W. McPherson
- Applicant: Wolfspeed, Inc.
- Applicant Address: US NC Durham
- Assignee: Wolfspeed, Inc.
- Current Assignee: Wolfspeed, Inc.
- Current Assignee Address: US NC Durham
- The original application number of the division: US17177641 2021.02.17
- Main IPC: H01L29/40
- IPC: H01L29/40

Abstract:
Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.
Public/Granted literature
- US12159909B2 Power semiconductor device with reduced strain Public/Granted day:2024-12-03
Information query
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