Invention Publication
- Patent Title: METHOD FOR MANUFACTURING SUBSTRATE WITH CHIPS, AND SUBSTRATE PROCESSING DEVICE
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Application No.: US18261898Application Date: 2022-01-18
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Publication No.: US20240079403A1Publication Date: 2024-03-07
- Inventor: Yoshihisa MATSUBARA , Yoshihiro TSUTSUMI , Yohei YAMASHITA
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Priority: JP 21013785 2021.01.29
- International Application: PCT/JP2022/001520 2022.01.18
- Date entered country: 2023-07-18
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L21/304 ; H01L21/67 ; H01L21/683 ; H01L25/065

Abstract:
A method of manufacturing a substrate with chips includes the following (A) and (B):
(A) preparing a stacked substrate, the stacked substrate including: a plurality of chips; a first substrate to which the plurality of chips are temporarily bonded; and a second substrate bonded to the first substrate via the plurality of chips; and
(B) separating the plurality of chips bonded to the first substrate and the second substrate, from the first substrate, in order to bond the plurality of chips to one surface of a third substrate including a device layer.
In this method, the first substrate, from which the plurality of chips are separated, includes alignment marks that are used to ensure alignment when the first substrate and the plurality of chips are bonded together, or that are used to measure misalignment after the first substrate and the plurality of chips are bonded together.
(A) preparing a stacked substrate, the stacked substrate including: a plurality of chips; a first substrate to which the plurality of chips are temporarily bonded; and a second substrate bonded to the first substrate via the plurality of chips; and
(B) separating the plurality of chips bonded to the first substrate and the second substrate, from the first substrate, in order to bond the plurality of chips to one surface of a third substrate including a device layer.
In this method, the first substrate, from which the plurality of chips are separated, includes alignment marks that are used to ensure alignment when the first substrate and the plurality of chips are bonded together, or that are used to measure misalignment after the first substrate and the plurality of chips are bonded together.
Information query
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