Integrated circuit structures having fin isolation regions recessed for gate contact are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A dielectric gate cut plug is between the gate structure and the dielectric structure. A recess is in the dielectric structure and in the dielectric gate cut plug. A conductive structure is in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.