Invention Publication
- Patent Title: MERGED TRENCHES SURROUNDED BY WIDER TRENCH FOR ISOLATING SEMICONDUCTOR DEVICES
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Application No.: US17977403Application Date: 2022-10-31
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Publication No.: US20240145293A1Publication Date: 2024-05-02
- Inventor: Hao YANG , Asad HAIDER , Guruvayurappan MATHUR , Abbas ALI , Alexei SADOVNIKOV , Umamaheswari AGHROAM
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L29/06
Abstract:
Active semiconductor devices in an integrated circuit are provided lateral electrical isolation by surrounding narrow deep trench isolation regions that are merged at shared portions of the narrow deep trench isolation regions. A wide deep trench isolation region laterally surrounds the merged narrow deep trench isolation regions.
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