公开(公告)号：US20240145293A1

公开(公告)日：2024-05-02

申请号：US17977403

申请日：2022-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hao YANG ,  Asad HAIDER ,  Guruvayurappan MATHUR ,  Abbas ALI ,  Alexei SADOVNIKOV ,  Umamaheswari AGHROAM

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/76237 ,  H01L29/0649

Abstract: Active semiconductor devices in an integrated circuit are provided lateral electrical isolation by surrounding narrow deep trench isolation regions that are merged at shared portions of the narrow deep trench isolation regions. A wide deep trench isolation region laterally surrounds the merged narrow deep trench isolation regions.

公开(公告)号：US20190304786A1

公开(公告)日：2019-10-03

申请号：US15944550

申请日：2018-04-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas ALI ,  Binghua HU ,  Stephanie L. HILBUN ,  Scott William JESSEN ,  Ronald CHIN ,  Jarvis Benjamin JACOBS

IPC: H01L21/266 ,  H01L29/66

Abstract: A method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing and exposing a pattern in a photoresist layer to radiation followed by etching to provide an opening; etching a portion of the anti-reflective coating below the opening; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent to grow an oxide region followed by removing the barrier layer; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.

公开(公告)号：US20150187632A1

公开(公告)日：2015-07-02

申请号：US14548812

申请日：2014-11-20

Applicant: Texas Instruments Incorporated

Inventor： Abbas ALI ,  Eric BEACH

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L28/24 ,  H01L21/7681 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step.

Abstract translation: 具有金属薄膜电阻器的集成电路，具有上覆蚀刻停止层。 一种通过添加一个光刻步骤在集成电路中形成金属薄膜电阻器的工艺。

公开(公告)号：US20190157142A1

公开(公告)日：2019-05-23

申请号：US16241143

申请日：2019-01-07

Applicant: Texas Instruments Incorporated

Inventor： Hong YANG ,  Abbas ALI ,  Yaping CHEN ,  Chao ZUO ,  Seetharaman SRIDHAR ,  Yunlong LIU

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L21/3213

Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.

公开(公告)号：US20180342416A1

公开(公告)日：2018-11-29

申请号：US15991938

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bradley David SUCHER ,  Bernard John FISCHER ,  Abbas ALI

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76237 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0649

Abstract: An electronic device includes a semiconductor substrate having a plurality of trenches formed therein. Each trench includes a sidewall having a doped region, a sidewall liner, and a filler material. The substrate has a slip density of less than 5 cm−2. The low slip density is achieved by a novel annealing protocol performed after implanting the dopant in the sidewall to repair damage and/or stress caused by the implant process.

公开(公告)号：US20240113156A1

公开(公告)日：2024-04-04

申请号：US17957983

申请日：2022-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Scott William JESSEN ,  Steven Lee PRINS ,  Sameer Prakash PENDHARKAR ,  Abbas ALI ,  Gregory Boyd SHINN

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/24 ,  H01L27/0629 ,  H01L21/0274

Abstract: A passive circuit component includes an edge having a low line edge roughness (LER). A method for manufacturing the passive circuit component includes a self-aligned double patterning (SADP) etch process using a tri-layer process flow. The tri-layer process flow includes use of an underlayer, hard mask, and photoresist. The passive circuit component made by this method achieves improved mismatch between like components due to the low LER.

公开(公告)号：US20190074193A1

公开(公告)日：2019-03-07

申请号：US15981725

申请日：2018-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas ALI ,  Dhishan KANDE ,  Qi-Zhong HONG ,  Young-Joon PARK ,  Kyle MCPHERSON

IPC: H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32136 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76885 ,  H01L23/53223

Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.