公开(公告)号：US20160233294A1

公开(公告)日：2016-08-11

申请号：US15098452

申请日：2016-04-14

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. BABCOCK ,  Alexei SADOVNIKOV

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8228 ,  H01L27/082

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/8228 ,  H01L21/82285 ,  H01L27/082 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/732

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

公开(公告)号：US20240145293A1

公开(公告)日：2024-05-02

申请号：US17977403

申请日：2022-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hao YANG ,  Asad HAIDER ,  Guruvayurappan MATHUR ,  Abbas ALI ,  Alexei SADOVNIKOV ,  Umamaheswari AGHROAM

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/76237 ,  H01L29/0649

Abstract: Active semiconductor devices in an integrated circuit are provided lateral electrical isolation by surrounding narrow deep trench isolation regions that are merged at shared portions of the narrow deep trench isolation regions. A wide deep trench isolation region laterally surrounds the merged narrow deep trench isolation regions.

公开(公告)号：US20210343860A1

公开(公告)日：2021-11-04

申请号：US17375598

申请日：2021-07-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei SADOVNIKOV ,  Natalia LAVROVSKAYA

IPC: H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L21/768 ,  H01L29/45 ,  H01L21/02 ,  H01L29/49 ,  H01L21/311 ,  H01L29/08 ,  H01L21/324

Abstract: An integrated circuit includes a transistor that has an collector region, a base region laterally surrounded by the collector region, and an emitter region laterally surrounded by the base region. A silicide layer on the emitter region is laterally spaced apart from the base region by an unsilicided ring. The emitter region is laterally spaced apart from a base contact region that may be covered by a dielectric layer such as a gate oxide layer.

公开(公告)号：US20230387260A1

公开(公告)日：2023-11-30

申请号：US17826872

申请日：2022-05-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sheldon Douglas HAYNIE ,  Alexei SADOVNIKOV

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3213

CPC classification number: H01L29/66681 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7816 ,  H01L21/32134 ,  H01L29/66628

Abstract: A method includes forming a gate on a semiconductor layer of a substrate. A hard mask is formed over the gate and the semiconductor layer to expose a portion of the semiconductor layer. The exposed portion of the semiconductor layer is isotropically etched away to form a recess having a depth. A first selective epitaxial growth of a first semiconductor material doped with a first dopant is performed on the semiconductor layer in the recess. A second selective epitaxial growth of a second semiconductor material doped with a second dopant is performed on the first semiconductor material in the recess. The hard mask is then removed.

公开(公告)号：US20190207017A1

公开(公告)日：2019-07-04

申请号：US15859292

申请日：2017-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei SADOVNIKOV ,  Natalia LAVROVSKAYA

IPC: H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L21/768 ,  H01L21/324 ,  H01L21/02 ,  H01L29/49 ,  H01L21/311 ,  H01L29/08 ,  H01L29/45

CPC classification number: H01L29/7393 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/31105 ,  H01L21/324 ,  H01L21/76889 ,  H01L29/0808 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66325

Abstract: A method to fabricate a transistor, the method comprising: implanting dopants in a semiconductor to form a collector region having majority carriers of a first type; implanting dopants with a first dosage and implanting dopants with a second dosage in the collector region to form a base region having majority carriers of a second type, wherein the second dosage is at a lower energy than the first dosage; forming a gate oxide on the base region; forming a gate material on the gate oxide; forming the gate material and the gate oxide to leave uncovered an emitter area of the base region; and implanting dopants in the emitter area to form an emitter region having majority carriers of the first type.

公开(公告)号：US20230317774A1

公开(公告)日：2023-10-05

申请号：US17710320

申请日：2022-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei SADOVNIKOV ,  Guruvayurappan S. MATHUR

IPC: H01L29/06 ,  H01L29/73 ,  H01L21/265 ,  H01L29/66 ,  H01L21/761

CPC classification number: H01L29/0619 ,  H01L29/73 ,  H01L21/26513 ,  H01L29/66234 ,  H01L21/761

Abstract: A method includes implanting dopant of a first conductivity type into an epitaxial layer of semiconductor material to form first and second false collector regions adjacent to the surface of the epitaxial layer. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer from dopant of a second conductivity type that is opposite the first conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

公开(公告)号：US20170309703A1

公开(公告)日：2017-10-26

申请号：US15647493

申请日：2017-07-12

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. BABCOCK ,  Alexei SADOVNIKOV

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/10 ,  H01L29/08 ,  H01L29/04 ,  H01L27/082 ,  H01L21/8228 ,  H01L21/762 ,  H01L21/308 ,  H01L21/306 ,  H01L29/16 ,  H01L29/732 ,  H01L21/266

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/8228 ,  H01L21/82285 ,  H01L27/082 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/732

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

公开(公告)号：US20230411501A1

公开(公告)日：2023-12-21

申请号：US18242919

申请日：2023-09-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei SADOVNIKOV ,  Natalia LAVROVSKAYA

IPC: H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L21/768 ,  H01L29/45 ,  H01L21/02 ,  H01L29/49 ,  H01L21/311 ,  H01L29/08 ,  H01L21/324

CPC classification number: H01L29/7393 ,  H01L29/66325 ,  H01L21/26513 ,  H01L21/76889 ,  H01L29/45 ,  H01L21/02164 ,  H01L29/4916 ,  H01L21/31105 ,  H01L29/0808 ,  H01L21/324

Abstract: An integrated circuit includes a transistor that has an collector region, a base region laterally surrounded by the collector region, and an emitter region laterally surrounded by the base region. A silicide layer on the emitter region is laterally spaced apart from the base region by an unsilicided ring. The emitter region is laterally spaced apart from a base contact region that may be covered by a dielectric layer such as a gate oxide layer.

公开(公告)号：US20190165129A1

公开(公告)日：2019-05-30

申请号：US15824665

申请日：2017-11-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei SADOVNIKOV ,  Natalia LAVROVSKAYA

IPC: H01L29/66 ,  H01L29/739

Abstract: A method to fabricate a transistor includes implanting dopants in a semiconductor to form a collector region having majority carriers of a first type, implanting dopants in the collector region to form a base region, forming a gate oxide on the base region, forming a gate material on the gate oxide, forming the gate material and the gate oxide to leave uncovered an emitter area of the base region, forming an emitter region, and forming a dielectric to cover a first area of the emitter region and a first sidewall of the gate material and the gate oxide while leaving uncovered a second area of the emitter region. Metal is deposited over the dielectric and the second area of the emitter region, and the semiconductor is annealed to form silicide in the second area of the emitter region.