发明公开
- 专利标题: SUBSTRATE GLASS CORE PATTERNING FOR CTV IMPROVEMENT AND LAYER COUNT REDUCTION
-
申请号: US18089489申请日: 2022-12-27
-
公开(公告)号: US20240215163A1公开(公告)日: 2024-06-27
- 发明人: Onur OZKAN , Jacob VEHONSKY , Vinith BEJUGAM , Nicholas S. HAEHN , Andrea NICOLAS FLORES , Mao-Feng TSENG
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H05K1/11
- IPC分类号: H05K1/11 ; H05K1/03 ; H05K1/18
摘要:
Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprise glass. In an embodiment, a via is provided through the substrate, where the via is electrically conductive. In an embodiment, a recess is formed into the first surface of the substrate, and a trace is embedded in the recess. In an embodiment, the trace is electrically conductive.
信息查询