公开(公告)号：US20230086649A1

公开(公告)日：2023-03-23

申请号：US17483621

申请日：2021-09-23

申请人： Intel Corporation

发明人： Onur OZKAN ,  Edvin CETEGEN ,  Steve CHO ,  Nicholas S. HAEHN ,  Jacob VEHONSKY

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/10

摘要： An apparatus is described. The apparatus includes I/O structures having pads and solder balls to couple with a semiconductor chip, wherein, a first subset of pads and/or solder balls of the pads and solder balls that approach the semiconductor chip during coupling of the semiconductor chip to the I/O structures are thinner than a second subset of pads and/or solder balls of the pads and solder balls that move away from the semiconductor chip during the coupling of the semiconductor chip to the I/O structures.

公开(公告)号：US20240079530A1

公开(公告)日：2024-03-07

申请号：US17903126

申请日：2022-09-06

申请人： Intel Corporation

发明人： Jacob VEHONSKY ,  Onur OZKAN ,  Vinith BEJUGAM ,  Mao-Feng TSENG ,  Nicholas HAEHN ,  Andrea NICOLAS FLORES ,  Ali LEHAF ,  Benjamin DUONG ,  Joshua STACEY

IPC分类号： H01L33/48 ,  H01L33/00 ,  H01L33/60 ,  H01L33/62

CPC分类号： H01L33/486 ,  H01L33/005 ,  H01L33/60 ,  H01L33/62 ,  H01L2933/0058 ,  H01L2933/0066

摘要： Embodiments of an integrated circuit (IC) package are disclosed. In some embodiments, the IC package includes a semiconductor die, a glass substrate, and a package substrate. The semiconductor die includes a micro light emitting diode (LED). The semiconductor die is at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to the semiconductor die to provide power to the micro LED. The package substrate that is coupled to the TGV.

公开(公告)号：US20230087810A1

公开(公告)日：2023-03-23

申请号：US17482852

申请日：2021-09-23

申请人： Intel Corporation

发明人： Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD ,  Oscar OJEDA ,  Bai NIE ,  Brandon C. MARIN ,  Gang DUAN ,  Jacob VEHONSKY ,  Onur OZKAN ,  Nicholas S. HAEHN

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00

摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

公开(公告)号：US20240215163A1

公开(公告)日：2024-06-27

申请号：US18089489

申请日：2022-12-27

申请人： Intel Corporation

发明人： Onur OZKAN ,  Jacob VEHONSKY ,  Vinith BEJUGAM ,  Nicholas S. HAEHN ,  Andrea NICOLAS FLORES ,  Mao-Feng TSENG

IPC分类号： H05K1/11 ,  H05K1/03 ,  H05K1/18

CPC分类号： H05K1/112 ,  H05K1/0306 ,  H05K1/183 ,  H01L23/49838

摘要： Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprise glass. In an embodiment, a via is provided through the substrate, where the via is electrically conductive. In an embodiment, a recess is formed into the first surface of the substrate, and a trace is embedded in the recess. In an embodiment, the trace is electrically conductive.

公开(公告)号：US20240079259A1

公开(公告)日：2024-03-07

申请号：US17901894

申请日：2022-09-02

申请人： Intel Corporation

发明人： Jacob VEHONSKY ,  Onur OZKAN ,  Vinith BEJUGAM ,  Mao-Feng TSENG ,  Andrea NICOLAS ,  Nicholas HAEHN

IPC分类号： H01L21/683 ,  B32B3/30 ,  B32B7/12 ,  B32B33/00 ,  B32B37/12 ,  H01L21/67

CPC分类号： H01L21/6835 ,  B32B3/30 ,  B32B7/12 ,  B32B33/00 ,  B32B37/12 ,  H01L21/67121 ,  B32B17/06 ,  H01L2221/68345

摘要： The present disclosure is directed to a system that uses a dual surface substrate carrier that includes a first transparent support with a first top surface and first bottom surface, a second transparent support with a second top surface and second bottom surface, and a reflective film positioned between and attached to the first transparent support and the second transparent support. The first transparent support has a first set of trenches configured in the first top surface that form a first set of ridges between the plurality of trenches and the second transparent support has a second set of trenches configured in the second top surface that form a second set of ridges between the plurality of trenches. The first transparent support is also configured with a first build surface and the second transparent support is also configured with a second build surface that are platforms for building package substrates.