公开(公告)号：US20230087810A1

公开(公告)日：2023-03-23

申请号：US17482852

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD ,  Oscar OJEDA ,  Bai NIE ,  Brandon C. MARIN ,  Gang DUAN ,  Jacob VEHONSKY ,  Onur OZKAN ,  Nicholas S. HAEHN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

公开(公告)号：US20210242107A1

公开(公告)日：2021-08-05

申请号：US16781563

申请日：2020-02-04

Applicant: Intel Corporation

Inventor： Wei LI ,  Edvin CETEGEN ,  Nicholas S. HAEHN ,  Mitul MODI ,  Nicholas NEAL

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/367

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

公开(公告)号：US20250106982A1

公开(公告)日：2025-03-27

申请号：US18372585

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Sashi S. KANDANUR ,  Mitchell PAGE ,  Nicholas S. HAEHN ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Steve S. CHO

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11

Abstract: Embodiments disclosed herein include glass cores with through glass vias (TGVs). In an embodiment, an apparatus comprises a solid glass layer with an opening through a thickness of the layer, and a via in the opening. In an embodiment, the via comprises a first portion along sidewalls of the opening, where the first portion has a first microstructure, and a second portion in the opening, where the first portion surrounds the second portion, and where the second portion has a second microstructure that is different than the first microstructure.

公开(公告)号：US20240215163A1

公开(公告)日：2024-06-27

申请号：US18089489

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Onur OZKAN ,  Jacob VEHONSKY ,  Vinith BEJUGAM ,  Nicholas S. HAEHN ,  Andrea NICOLAS FLORES ,  Mao-Feng TSENG

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/18

CPC classification number: H05K1/112 ,  H05K1/0306 ,  H05K1/183 ,  H01L23/49838

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprise glass. In an embodiment, a via is provided through the substrate, where the via is electrically conductive. In an embodiment, a recess is formed into the first surface of the substrate, and a trace is embedded in the recess. In an embodiment, the trace is electrically conductive.

公开(公告)号：US20170140076A1

公开(公告)日：2017-05-18

申请号：US14942749

申请日：2015-11-16

Applicant: Intel Corporation

Inventor： Nicholas S. HAEHN ,  Sashi S. KANDANUR

IPC: G06F17/50 ,  G06F17/10

CPC classification number: C25D17/008 ,  C25D7/005

Abstract: A method including running a simulated plating process on a substrate using a base shield, the base shield including a plurality of openings therethrough defining an array including two coordinates; after running the simulated plating process, determining if a predetermined criterion for the simulated plating process is satisfied; and if the predetermined criterion is not satisfied, adjusting one or more of the plurality of openings. A machine readable medium including program instructions that when executed by a controller cause the controller to perform a method including running a simulated plating process on a substrate using a base shield, the base shield including a plurality of openings therethrough defining an array including two coordinates; after running the simulated plating process, determining if a predetermined criterion for the simulated plating process is satisfied; and if the predetermined criterion is not satisfied, adjusting one or more of the plurality of openings.

公开(公告)号：US20250112140A1

公开(公告)日：2025-04-03

申请号：US18374609

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rahul BHURE ,  Mitchell PAGE ,  Joseph PEOPLES ,  Jieying KONG ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Bainye Francoise ANGOUA ,  Yosef KORNBLUTH ,  Daniel ROSALES-YEOMANS ,  Joshua STACEY ,  Aaditya Anand CANDADAI ,  Yonggang Yong LI ,  Tchefor NDUKUM ,  Scott COATNEY ,  Gang DUAN ,  Jesse JONES ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Dilan SENEVIRATNE ,  Matthew ANDERSON

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15

Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a core with a first width, and the core comprises a glass layer. In an embodiment, a via is provided through a thickness of the core, where the via is electrically conductive. In an embodiment, a first layer is provided over the core, where the first layer comprises a second width that is smaller than the first width. In an embodiment, a second layer is provided under the core, where the second layer comprises a third width that is smaller than the first width.

公开(公告)号：US20230343723A1

公开(公告)日：2023-10-26

申请号：US18216005

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Nicholas NEAL ,  Nicholas S. HAEHN ,  Sergio CHAN ARGUEDAS ,  Edvin CETEGEN ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L23/562 ,  H01L23/5381 ,  H01L23/3675

Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.

公开(公告)号：US20230238355A1

公开(公告)日：2023-07-27

申请号：US18127539

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Wei LI ,  Edvin CETEGEN ,  Nicholas S. HAEHN ,  Ram S. VISWANATH ,  Nicholas NEAL ,  Mitul MODI

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/78 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US20230086649A1

公开(公告)日：2023-03-23

申请号：US17483621

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Onur OZKAN ,  Edvin CETEGEN ,  Steve CHO ,  Nicholas S. HAEHN ,  Jacob VEHONSKY

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/10

Abstract: An apparatus is described. The apparatus includes I/O structures having pads and solder balls to couple with a semiconductor chip, wherein, a first subset of pads and/or solder balls of the pads and solder balls that approach the semiconductor chip during coupling of the semiconductor chip to the I/O structures are thinner than a second subset of pads and/or solder balls of the pads and solder balls that move away from the semiconductor chip during the coupling of the semiconductor chip to the I/O structures.

公开(公告)号：US20210035921A1

公开(公告)日：2021-02-04

申请号：US16526087

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Nicholas NEAL ,  Nicholas S. HAEHN ,  Sergio CHAN ARGUEDAS ,  Edvin CETEGEN ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.