Invention Publication
- Patent Title: FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING MULTI-LAYER MOLYBDENUM METAL GATE STACK
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Application No.: US18129651Application Date: 2023-03-31
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Publication No.: US20240332394A1Publication Date: 2024-10-03
- Inventor: David N. GOLDSTEIN , David J. TOWNER , Dax M. CRUM , Omair SAADAT , Dan S. LAVRIC , Orb ACTON , Tongtawee WACHARASINDHU , Anand S. MURTHY , Tahir GHANI
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L27/092 ; H01L29/06 ; H01L29/40 ; H01L29/423 ; H01L29/66 ; H01L29/775

Abstract:
Gate-all-around integrated circuit structures having a multi-layer molybdenum metal gate stack are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A PMOS gate stack is over the first vertical arrangement of horizontal nanowires, the PMOS gate stack having a multi-layer molybdenum structure on a first gate dielectric. An NMOS gate stack is over the second vertical arrangement of horizontal nanowires, the NMOS gate stack having the multi-layer molybdenum structure or an N-type conductive layer on a second gate dielectric.
Information query
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