公开(公告)号：US20220416050A1

公开(公告)日：2022-12-29

申请号：US17359327

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Cory BOMBERGER ,  Gilbert DEWEY ,  Anand S. MURTHY ,  Mauro KOBRINSKY ,  Rushabh SHAH ,  Chi-Hing CHOI ,  Harold W. KENNEL ,  Omair SAADAT ,  Adedapo A. ONI ,  Nazila HARATIPOUR ,  Tahir GHANI

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

公开(公告)号：US20220093648A1

公开(公告)日：2022-03-24

申请号：US17030333

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  Omair SAADAT ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L27/12 ,  H01L21/84

Abstract: Gate-all-around integrated circuit structures having additive metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer over a first gate dielectric including a high-k dielectric layer on a first dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer over a second gate dielectric including the high-k dielectric layer on a second dipole material layer.

公开(公告)号：US20240332394A1

公开(公告)日：2024-10-03

申请号：US18129651

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： David N. GOLDSTEIN ,  David J. TOWNER ,  Dax M. CRUM ,  Omair SAADAT ,  Dan S. LAVRIC ,  Orb ACTON ,  Tongtawee WACHARASINDHU ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/4908 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having a multi-layer molybdenum metal gate stack are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A PMOS gate stack is over the first vertical arrangement of horizontal nanowires, the PMOS gate stack having a multi-layer molybdenum structure on a first gate dielectric. An NMOS gate stack is over the second vertical arrangement of horizontal nanowires, the NMOS gate stack having the multi-layer molybdenum structure or an N-type conductive layer on a second gate dielectric.

公开(公告)号：US20240429238A1

公开(公告)日：2024-12-26

申请号：US18825952

申请日：2024-09-05

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  Omair SAADAT ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.

公开(公告)号：US20220093598A1

公开(公告)日：2022-03-24

申请号：US17031832

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  Omair SAADAT ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.