Invention Publication
- Patent Title: 3D NAND CELLS WITH ENHANCED ERASE SPEED THROUGH DIPOLE ENGINEERING AND METHODS OF MAKING THE SAME
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Application No.: US18630142Application Date: 2024-04-09
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Publication No.: US20240365551A1Publication Date: 2024-10-31
- Inventor: Chang Seok Kang , Steven C. H. Hung , Hsueh Chung Chen , Naomi Yoshida , Sung-Kwan Kang , Balasubramanian Pranatharthiharan
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: H10B43/35
- IPC: H10B43/35 ; H01L21/67 ; H01L23/528 ; H01L23/532 ; H10B43/20
Abstract:
Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of metal-and-oxygen-containing material may include a first metal. The structures may include a second layer of metal-and-oxygen-containing material disposed within the first layer of metal-and-oxygen-containing material. The second layer of metal-and-oxygen-containing material may include a second metal. The structures may include a gate disposed within the second layer of metal-and-oxygen-containing material.
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