公开(公告)号：US20240365551A1

公开(公告)日：2024-10-31

申请号：US18630142

申请日：2024-04-09

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Steven C. H. Hung ,  Hsueh Chung Chen ,  Naomi Yoshida ,  Sung-Kwan Kang ,  Balasubramanian Pranatharthiharan

IPC: H10B43/35 ,  H01L21/67 ,  H01L23/528 ,  H01L23/532 ,  H10B43/20

CPC classification number: H10B43/35 ,  H01L21/67161 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53257 ,  H10B43/20

Abstract: Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of metal-and-oxygen-containing material may include a first metal. The structures may include a second layer of metal-and-oxygen-containing material disposed within the first layer of metal-and-oxygen-containing material. The second layer of metal-and-oxygen-containing material may include a second metal. The structures may include a gate disposed within the second layer of metal-and-oxygen-containing material.

公开(公告)号：US20230420232A1

公开(公告)日：2023-12-28

申请号：US18243436

申请日：2023-09-07

Applicant: Applied Materials, Inc.

Inventor： Tomohiko Kitajima ,  Ning Li ,  Chang Seok Kang ,  Naomi Yoshida

IPC: H01J37/32 ,  C23C16/34 ,  C23C16/38 ,  H01L21/67 ,  C23C16/36 ,  H01L21/02 ,  C23C16/02 ,  C23C16/56

CPC classification number: H01J37/32899 ,  C23C16/342 ,  C23C16/38 ,  C23C16/345 ,  H01L21/67167 ,  C23C16/36 ,  H01L21/0234 ,  C23C16/0227 ,  C23C16/56 ,  H01L21/0217 ,  H01J2237/20278 ,  H01J2237/336 ,  H01J2237/335 ,  H01J37/32816 ,  H01J2237/332

Abstract: Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.

公开(公告)号：US11282936B2

公开(公告)日：2022-03-22

申请号：US17020372

申请日：2020-09-14

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Nam Sung Kim ,  Bingxi Sun Wood ,  Naomi Yoshida ,  Sheng-Chin Kung ,  Miao Jin

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1.

公开(公告)号：US10608097B2

公开(公告)日：2020-03-31

申请号：US16033880

申请日：2018-07-12

Applicant: Applied Materials, Inc.

Inventor： Paul F. Ma ,  Seshadri Ganguli ,  Shih Chung Chen ,  Rajesh Sathiyanarayanan ,  Atashi Basu ,  Lin Dong ,  Naomi Yoshida ,  Sang Ho Yu ,  Liqi Wu

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/40 ,  H01L29/49 ,  H01L21/285 ,  H01L21/8234 ,  H01L21/8238

Abstract: Film stacks and methods of forming film stacks including a high-k dielectric layer on a substrate, a high-k capping layer on the high-k dielectric layer, an n-metal layer on the high-k capping layer and an n-metal capping layer on the n-metal layer. The n-metal layer having an aluminum rich interface adjacent the high-k capping layer.

公开(公告)号：US10573719B2

公开(公告)日：2020-02-25

申请号：US15279257

申请日：2016-09-28

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Benjamin Colombeau ,  Michael Chudzik

IPC: H01L21/76 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786 ,  H01L29/15

Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US10262858B2

公开(公告)日：2019-04-16

申请号：US15496982

申请日：2017-04-25

Applicant: Applied Materials, Inc. ,  The Regents of the University of California

Inventor： Naomi Yoshida ,  Lin Dong ,  Andrew Kummel ,  Jessica Kachian ,  Mary Edmonds ,  Steve Wolf

IPC: H01L21/02

Abstract: Embodiments described herein relate to semiconductor and metal substrate surface preparation and controlled growth methods. An example application is formation of an atomic layer deposition (ALD) control layer as a diffusion barrier or gate dielectric layer and subsequent ALD processing. Embodiments described herein are believed to be advantageously utilized concerning gate oxide deposition, diffusion barrier deposition, surface functionalization, surface passivation, and oxide nucleation, among other processes. More specifically, embodiments described herein provide for silicon nitride ALD processes which functionalize, passivate, and nucleate a SiNx monolayer at temperatures below about 300° C.

公开(公告)号：US09460920B1

公开(公告)日：2016-10-04

申请号：US14755099

申请日：2015-06-30

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Benjamin Colombeau ,  Michael Chudzik

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/42392 ,  H01L29/66742

Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract translation: 本文描述的实施例通常涉及用于水平门全周（hGAA）隔离的方法和装置。 可以在衬底上形成包括布置在交替堆叠的层中的不同材料的超晶格结构。 不同的材料可以是含硅材料和一种或多种III / V材料。 在一个实施例中，超晶格结构的至少一个层可以被氧化以形成邻近衬底的掩埋氧化物层。

公开(公告)号：US12062545B2

公开(公告)日：2024-08-13

申请号：US17339454

申请日：2021-06-04

Applicant: Applied Materials, Inc.

Inventor： Ilanit Fisher ,  Chi-Chou Lin ,  Kedi Wu ,  Wen Ting Chen ,  Shih Chung Chen ,  Srinivas Gandikota ,  Mandyam Sriram ,  Chenfei Shen ,  Naomi Yoshida ,  He Ren

IPC: H01L21/285 ,  C23C16/02 ,  C23C16/04 ,  C23C16/14 ,  C23C16/455 ,  H01L21/02

CPC classification number: H01L21/28568 ,  C23C16/0227 ,  C23C16/04 ,  C23C16/14 ,  C23C16/45553 ,  H01L21/02068

Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.

公开(公告)号：US11830725B2

公开(公告)日：2023-11-28

申请号：US17153450

申请日：2021-01-20

Applicant: Applied Materials, Inc.

Inventor： Naomi Yoshida ,  He Ren ,  Hao Jiang ,  Chenfei Shen ,  Chi-Chou Lin ,  Hao Chen ,  Xuesong Lu ,  Mehul B. Naik

IPC: H01L21/02 ,  H01L21/28 ,  B08B5/02 ,  H01L29/66 ,  H01L21/3205

CPC classification number: H01L21/02057 ,  B08B5/02 ,  H01L21/28026 ,  H01L21/32051 ,  H01L29/66795

Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.

公开(公告)号：US11615984B2

公开(公告)日：2023-03-28

申请号：US16848784

申请日：2020-04-14

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi You ,  He Ren ,  Naomi Yoshida ,  Nikolaos Bekiaris ,  Mehul Naik ,  Martin Jay Seamons ,  Jingmei Liang ,  Mei-Yee Shek

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.