公开(公告)号：US20240365551A1

公开(公告)日：2024-10-31

申请号：US18630142

申请日：2024-04-09

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Steven C. H. Hung ,  Hsueh Chung Chen ,  Naomi Yoshida ,  Sung-Kwan Kang ,  Balasubramanian Pranatharthiharan

IPC: H10B43/35 ,  H01L21/67 ,  H01L23/528 ,  H01L23/532 ,  H10B43/20

CPC classification number: H10B43/35 ,  H01L21/67161 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53257 ,  H10B43/20

Abstract: Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of metal-and-oxygen-containing material may include a first metal. The structures may include a second layer of metal-and-oxygen-containing material disposed within the first layer of metal-and-oxygen-containing material. The second layer of metal-and-oxygen-containing material may include a second metal. The structures may include a gate disposed within the second layer of metal-and-oxygen-containing material.

公开(公告)号：US20240407170A1

公开(公告)日：2024-12-05

申请号：US18659256

申请日：2024-05-09

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Raman Gaire ,  Hsueh Chung Chen ,  In Soo Jung ,  Houssam Lazkani ,  Hui Zhao ,  Liu Jiang ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi

IPC: H10B43/40 ,  H10B41/35 ,  H10B41/49 ,  H10B43/23 ,  H10B43/35

Abstract: Methods and structures to achieve low voltage (LV) and high voltage (HV) scale-down by suppressing the short channel effect of LV as well as increasing breakdown voltage of HV transistor are provided. A semiconductor device comprises a first transistor comprising a first well region of a first conductivity type, a first gate region disposed above the first well region, and a first contact region including a first epitaxial semiconductor adjacent to the first gate region; and a second transistor comprising a second well region of a second conductivity, a second gate region disposed above the second well region, and a second contact region including a second epitaxial semiconductor adjacent to the second gate region.

公开(公告)号：US20250022935A1

公开(公告)日：2025-01-16

申请号：US18761490

申请日：2024-07-02

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Raghuveer Satya Makala ,  Naomi Yoshida ,  Hsueh Chung Chen ,  Balasubramanian Pranatharthiharan

IPC: H01L29/49 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Methods of manufacturing memory devices are provided. The method comprises forming a first epitaxial layer on a substrate; and forming a memory array on the first epitaxial layer, the memory array comprising a memory stack of alternating layers of an oxide material and a metal material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack, and a slit filled with a fill material adjacent to the at least one memory cell.

公开(公告)号：US20240249934A1

公开(公告)日：2024-07-25

申请号：US18626864

申请日：2024-04-04

Applicant: Applied Materials, Inc.

Inventor： Naomi Yoshida ,  Bhaskar Jyoti Bhuyan ,  Hsueh Chung Chen ,  Scott A. DeVries ,  Raghuveer Satya Makala

IPC: H01L21/02 ,  C23C16/455 ,  H01L21/768

CPC classification number: H01L21/0217 ,  C23C16/45544 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/02326 ,  H01L21/76831 ,  H01L21/02046 ,  H01L21/02052

Abstract: Methods of manufacturing electronic devices, e.g., logic devices or memory devices, are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; pre-treating the top surface of the film stack to form a treated surface; exposing the treated surface to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.