Invention Application
- Patent Title: SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS
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Application No.: US18204864Application Date: 2023-06-01
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Publication No.: US20240404917A1Publication Date: 2024-12-05
- Inventor: Sikandar Abbas , Chanaka Munasinghe , Leonard Guler , Reza Bayati , Madeleine Stolt , Makram Abd El Qader , Pratik Patel , Anindya Dasgupta
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/768 ; H01L23/528

Abstract:
Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.
Information query
IPC分类: