公开(公告)号：US20240404917A1

公开(公告)日：2024-12-05

申请号：US18204864

申请日：2023-06-01

Applicant: Intel Corporation

Inventor： Sikandar Abbas ,  Chanaka Munasinghe ,  Leonard Guler ,  Reza Bayati ,  Madeleine Stolt ,  Makram Abd El Qader ,  Pratik Patel ,  Anindya Dasgupta

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528

Abstract: Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.

公开(公告)号：US20230290825A1

公开(公告)日：2023-09-14

申请号：US17693136

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Sean Pursel ,  Raghuram Gandikota ,  Sikandar Abbas ,  Tsuan-Chung Chang ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Elliot N. Tan

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/41733 ,  H01L29/66742 ,  H01L27/0886

Abstract: Integrated circuit structures having backside self-aligned conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is on and in contact with the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.

公开(公告)号：US20230275124A1

公开(公告)日：2023-08-31

申请号：US17681263

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Gilbert Dewey ,  Saurabh Morarka ,  Sikandar Abbas ,  Mohammad Hasan

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L27/088

Abstract: Techniques are provided herein to form semiconductor devices having epitaxial diffusion regions (e.g., source and/or drain regions) wrapped by a conductive contact. In an example, a semiconductor device includes a source or drain region and a conductive layer that extends around the source or drain region such that the conductive layer at least contacts the sidewalls of the source or drain region or wraps completely around the source or drain region. In some examples, a conducive contact extends upward through a thickness of an adjacent dielectric layer and contacts the conductive layer from below, thus forming a backside contact. By forming a conductive layer around multiple sides of the source or drain region (rather than just contacting a top or bottom surface) more surface area of the source or drain region is contacted thus providing an improved ohmic contact and a lower overall contact resistance.