公开(公告)号：US20240404917A1

公开(公告)日：2024-12-05

申请号：US18204864

申请日：2023-06-01

Applicant: Intel Corporation

Inventor： Sikandar Abbas ,  Chanaka Munasinghe ,  Leonard Guler ,  Reza Bayati ,  Madeleine Stolt ,  Makram Abd El Qader ,  Pratik Patel ,  Anindya Dasgupta

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528

Abstract: Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.

公开(公告)号：US20220006459A1

公开(公告)日：2022-01-06

申请号：US17479963

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Miguel Bautista Gabriel ,  Sriram Vangal ,  Patrick Koeberl ,  Pratik Patel ,  Muhammad Khellah ,  James Tschanz ,  Carlos Tokunaga ,  Suyoung Bang

IPC: H03K19/17768 ,  H03K19/17784 ,  H03K19/0185 ,  H03K19/0175 ,  G01R31/28

Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

公开(公告)号：US12237832B2

公开(公告)日：2025-02-25

申请号：US17479963

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Miguel Bautista Gabriel ,  Sriram Vangal ,  Patrick Koeberl ,  Pratik Patel ,  Muhammad Khellah ,  James Tschanz ,  Carlos Tokunaga ,  Suyoung Bang

IPC: H03K19/177 ,  G01R31/28 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/17768 ,  H03K19/17784

Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

公开(公告)号：US11828776B2

公开(公告)日：2023-11-28

申请号：US16829582

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Pratik Patel ,  Sriram Vangal ,  Patrick Koeberl ,  Miguel Bautista Gabriel ,  James Tschanz ,  Carlos Tokunaga

IPC: G01R19/165 ,  G06F21/75 ,  H03K5/00 ,  H03K3/037 ,  H03K19/21 ,  H01L23/00 ,  G06F11/07

CPC classification number: G01R19/16533 ,  G06F11/0736 ,  G06F11/0757 ,  G06F11/0772 ,  G06F21/755 ,  H01L23/576 ,  H03K3/037 ,  H03K5/00 ,  H03K19/21 ,  H03K2005/00058 ,  H03K2005/00078

Abstract: A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

公开(公告)号：US20230320057A1

公开(公告)日：2023-10-05

申请号：US17711875

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Leonard Guler ,  Mohit Haran ,  Smita Shridharan ,  Reken Patel ,  Charles Wallace ,  Chanaka Munasinghe ,  Pratik Patel

IPC: H01L27/11 ,  H01L27/02 ,  G11C11/412 ,  H01L21/768 ,  H01L23/522 ,  H01L29/423

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  G11C11/412 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/42392

Abstract: Integrated circuit (IC) devices include transistors with gate, source and drain contact metallization, some of which are jumpered together by a metallization that is recessed below a height of other metallization that is not jumpered. The jumper metallization may provide a local interconnect between terminals of one transistor or adjacent transistors, for example between a gate of one transistor and a source/drain of another transistor. The jumper metallization may not induce the same pitch constraints faced by interconnect line metallization levels employed for more general interconnection. In some examples, a static random-access memory (SRAM) bit-cell includes a jumper metallization joining two transistors of the cell to reduce cell height for a given feature patterning capability.

公开(公告)号：US12027417B2

公开(公告)日：2024-07-02

申请号：US16913320

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Suresh Vishwanath ,  Yulia Tolstova ,  Pratik Patel ,  Szuya S. Liao ,  Anand S. Murthy

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/76834 ,  H01L21/02532 ,  H01L21/28255 ,  H01L21/3215 ,  H01L21/76831 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66628

Abstract: Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.

公开(公告)号：US11901457B2

公开(公告)日：2024-02-13

申请号：US16700431

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Rahul Pandey ,  Rishabh Mehandru ,  Anupama Bowonder ,  Pratik Patel

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66795

Abstract: Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20230207560A1

公开(公告)日：2023-06-29

申请号：US17561244

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Cory C. Bomberger ,  Nicholas Minutillo ,  Ryan Cory Haislmaier ,  Yulia Tolstova ,  Yoon Jung Chang ,  Tahir Ghani ,  Szuya S. Liao ,  Anand Murthy ,  Pratik Patel

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/66795 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823412

Abstract: An integrated circuit (IC) structure, an IC device, an IC device assembly, and a method of forming the same. The IC structure includes a transistor device on a substrate comprising: a gate structure including a metal, the gate structure on a channel structure; a source structure in a first trench at a first side of the gate structure; a drain structure in a second trench at a second side of the gate structure; a capping layer on individual ones of the source structure and of the drain structure. The capping layer comprising a semiconductor material of a same group as a semiconductor material of a corresponding one of the source structure or of the drain structure, wherein an isotope of a p-type dopant in the capping layer represents an atomic percentage of at least about 95% of a p-type isotope content of the capping layer; and metal contact structures coupled to respective ones of the source structure and of the drain structure.

公开(公告)号：US20230095191A1

公开(公告)日：2023-03-30

申请号：US17485149

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Koustav Ganguly ,  Ryan Keech ,  Anand Murthy ,  Mohammad Hasan ,  Pratik Patel ,  Tahir Ghani ,  Subrina Rafique

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66

Abstract: Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials.

公开(公告)号：US20200226295A1

公开(公告)日：2020-07-16

申请号：US16829582

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Pratik Patel ,  Sriram Vangal ,  Patrick Koeberl ,  Miguel Bautista Gabriel ,  James Tschanz ,  Carlos Tokunaga

IPC: G06F21/75 ,  H03K5/00 ,  H03K3/037 ,  H03K19/21 ,  H01L23/00 ,  G06F11/07 ,  G01R19/165

Abstract: A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.