Invention Application
- Patent Title: SEMICONDUCTOR DEVICE FOR PERFORMING DATA REDUCTION FOR PROCESSING ARRAYS
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Application No.: US18217079Application Date: 2023-06-30
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Publication No.: US20250004963A1Publication Date: 2025-01-02
- Inventor: William Peter Ehrett , Anthony Gutierrez , Vedula Venkata Srikant Bharadwaj , Karthik Ramu Sangaiah , Prachi Shukla , Sriseshan Srikanth , Ganesh Dasika , John Kalamatianos
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F13/36
- IPC: G06F13/36

Abstract:
A semiconductor device, referred to herein as a Globally Interconnected Operations (GIO) layer, provides global operations in the form of global data reduction for one or more PE arrays. The GIO layer includes processing elements that perform global data reduction on processing results from one or more PE arrays. The GIO layer includes connectors that allow it to be arranged in a 3D stack with one or more PE arrays, for example, on top of or beneath a PE array. This allows reduction operations to be implemented across PE arrays using an efficient topology with superior flexibility, scalability, latency and/or power characteristics that is customizable for particular use cases at assembly time, without requiring costly and time-consuming redesign of PE arrays, and without being constrained by particular PE array designs.
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