公开(公告)号：US12169758B2

公开(公告)日：2024-12-17

申请号：US17491304

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Salonik Resch ,  Anthony Gutierrez ,  Yasuko Eckert ,  Vedula Venkata Srikant Bharadwaj ,  Mark H. Oskin

IPC: G06F9/48 ,  G06F11/36 ,  G06N10/00

Abstract: An electronic device includes a quantum processor having a plurality of qubits and a processor. The processor runs a plurality of instances of a quantum program substantially in parallel on the quantum processor using a separate set of qubits from among the plurality of qubits for each instance of the quantum program. The processor then acquires an output for each instance of the quantum program from the quantum processor. The processor next uses the outputs for generating an output of the quantum program.

公开(公告)号：US20230094508A1

公开(公告)日：2023-03-30

申请号：US17491304

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Salonik Resch ,  Anthony Gutierrez ,  Yasuko Eckert ,  Vedula Venkata Srikant Bharadwaj ,  Mark H. Oskin

IPC: G06N10/00 ,  G06F11/36 ,  G06F9/48

Abstract: An electronic device includes a quantum processor having a plurality of qubits and a processor. The processor runs a plurality of instances of a quantum program substantially in parallel on the quantum processor using a separate set of qubits from among the plurality of qubits for each instance of the quantum program. The processor then acquires an output for each instance of the quantum program from the quantum processor. The processor next uses the outputs for generating an output of the quantum program.

公开(公告)号：US11550627B2

公开(公告)日：2023-01-10

申请号：US17215171

申请日：2021-03-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony Gutierrez ,  Sooraj Puthoor

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/38

Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

公开(公告)号：US11086809B2

公开(公告)日：2021-08-10

申请号：US16693638

申请日：2019-11-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony Gutierrez

IPC: G06F13/36 ,  G06F13/362 ,  G06F11/34 ,  G06F11/30

Abstract: Data transfer acceleration includes receiving, by a data transfer accelerator in a first node of a plurality of nodes, from a second node of the plurality of nodes, a request for data in a second state, wherein the second node stores an instance of the data in a first state; generating a message including one or more operations to transform the data from the first state to the second state; and sending the message to the second node in response to the request.

公开(公告)号：US12131186B2

公开(公告)日：2024-10-29

申请号：US17993490

申请日：2022-11-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony Gutierrez ,  Sooraj Puthoor

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/3877 ,  G06F9/542 ,  G06F9/545 ,  G06F9/546

Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

公开(公告)号：US11875425B2

公开(公告)日：2024-01-16

申请号：US17134904

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sooraj Puthoor ,  Bradford Beckmann ,  Nuwan Jayasena ,  Anthony Gutierrez

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/30 ,  G06F9/54

CPC classification number: G06T1/20 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/545 ,  G06T2210/52

Abstract: Implementing heterogeneous wavefronts on a graphics processing unit (GPU) is disclosed. A scheduler assigns heterogeneous wavefronts for execution on a compute unit of a processing device. The heterogeneous wavefronts include different types of wavefronts such as vector compute wavefronts and service-level wavefronts that vary in resource requirements and instruction sets. As one example, heterogeneous wavefronts may include scalar wavefronts and vector compute wavefronts that execute on scalar units and vector units, respectively. Distinct sets of instructions are executed for the heterogeneous wavefronts on the compute unit. Heterogeneous wavefronts are processed in the same pipeline of the processing device.

公开(公告)号：US20220100563A1

公开(公告)日：2022-03-31

申请号：US17037727

申请日：2020-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony Gutierrez ,  Vedula Venkata Srikant Bharadwaj ,  Yasuko Eckert ,  Mark H. Oskin

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/30 ,  G06F9/4401

Abstract: A dynamically configurable overprovisioned microprocessor optimally supports a variety of different compute application workloads and with the capability to tradeoff among compute performance, energy consumption, and clock frequency on a per-compute application basis, using general-purpose microprocessor designs. In some embodiments, the overprovisioned microprocessor comprises a physical compute resource and a dynamic configuration logic configured to: detect an activation-warranting operating condition; undarken the physical compute resource responsive to detecting the activation-warranting operating condition; detect a configuration-warranting operating condition; and configure the overprovisioned microprocessor to use the undarkened physical compute resource responsive to detecting the configuration-warranting operating condition.

公开(公告)号：US12079145B2

公开(公告)日：2024-09-03

申请号：US18103240

申请日：2023-01-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Max Ruttenberg ,  Vendula Venkata Srikant Bharadwaj ,  Yasuko Eckert ,  Anthony Gutierrez ,  Mark H. Oskin

IPC: G06F13/16 ,  G11C11/4076

CPC classification number: G06F13/1668 ,  G11C11/4076

Abstract: A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.

公开(公告)号：US11720993B2

公开(公告)日：2023-08-08

申请号：US16138708

申请日：2018-09-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony Gutierrez ,  Muhammad Amber Hassaan ,  Sooraj Puthoor

IPC: G06F12/02 ,  G06T1/60 ,  G06F9/30 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F9/30098 ,  G06F12/02 ,  G06F12/023 ,  G06T1/20

Abstract: A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.

公开(公告)号：US20230153218A1

公开(公告)日：2023-05-18

申请号：US17526218

申请日：2021-11-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Shrikanth Ganapathy ,  Yasuko Eckert ,  Anthony Gutierrez ,  Karthik Ramu Sangaiah ,  Vedula Venkata Srikant Bharadwaj

IPC: G06F11/30 ,  G06F15/80

CPC classification number: G06F11/3051 ,  G06F15/80 ,  G06F11/3024

Abstract: A processor includes a controller and plurality of chiplets, each chiplet including a plurality of processor cores. The controller provides chiplet-level performance information for the chiplets that identifies a performance of each chiplet at each of a plurality of performance levels for specified sets of processor cores on that chiplet. The controller receives an identification of one or more selected chiplets from among the plurality of chiplets for which a specified number of processor cores are to be configured at a given performance level, the one or more selected chiplets having been selected based on the chiplet-level performance information and performance requirements. The controller configures the specified number of processor cores of the one or more selected chiplets at the given performance level. A task is then run on the specified number of processor cores of the one or more selected chiplets at the given performance level.