公开(公告)号：US20250004963A1

公开(公告)日：2025-01-02

申请号：US18217079

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： William Peter Ehrett ,  Anthony Gutierrez ,  Vedula Venkata Srikant Bharadwaj ,  Karthik Ramu Sangaiah ,  Prachi Shukla ,  Sriseshan Srikanth ,  Ganesh Dasika ,  John Kalamatianos

IPC: G06F13/36

Abstract: A semiconductor device, referred to herein as a Globally Interconnected Operations (GIO) layer, provides global operations in the form of global data reduction for one or more PE arrays. The GIO layer includes processing elements that perform global data reduction on processing results from one or more PE arrays. The GIO layer includes connectors that allow it to be arranged in a 3D stack with one or more PE arrays, for example, on top of or beneath a PE array. This allows reduction operations to be implemented across PE arrays using an efficient topology with superior flexibility, scalability, latency and/or power characteristics that is customizable for particular use cases at assembly time, without requiring costly and time-consuming redesign of PE arrays, and without being constrained by particular PE array designs.

公开(公告)号：US20250103395A1

公开(公告)日：2025-03-27

申请号：US18476071

申请日：2023-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford Beckmann ,  Matthew David Sinclair ,  Vinay Bharadwaj Ramakrishnaiah ,  William Peter Ehrett

IPC: G06F9/50

Abstract: A computer-implemented method for dynamic resource management can include evaluating, by at least one processor, whether a priority of one or more processes associated with a request for one or more shared resources meets a threshold condition. The method can additionally include determining, by the at least one processor and in response to an evaluation that the priority meets the threshold condition, whether the one or more shared resources is available to meet the request. The method can further include completing, by the at least one processor and in response to a determination that the one or more shared resources is available, execution of the one or more processes. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240330045A1

公开(公告)日：2024-10-03

申请号：US18194001

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： William Peter Ehrett ,  Vinay Bharadwaj Ramakrishnaiah ,  Bradford M. Beckmann

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/3885

Abstract: A technique for scheduling executing items on a highly parallel processing architecture is provided. The technique includes identifying a plurality of execution items that share data, as indicated by having matching commonality metadata; identifying an execution unit for executing the plurality of execution items together; and scheduling the plurality of execution items for execution together on the execution unit.