发明授权
- 专利标题: Ram retention during power up and power down
- 专利标题(中): 上电和断电时的Ram保持
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申请号: US884790申请日: 1978-03-09
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公开(公告)号: US4145761A公开(公告)日: 1979-03-20
- 发明人: Thomas G. Gunter , Fuad H. Musa , Pern Shaw , Michael F. Wiles
- 申请人: Thomas G. Gunter , Fuad H. Musa , Pern Shaw , Michael F. Wiles
- 申请人地址: IL Schaumburg
- 专利权人: Motorola Inc.
- 当前专利权人: Motorola Inc.
- 当前专利权人地址: IL Schaumburg
- 主分类号: G06F12/16
- IPC分类号: G06F12/16 ; G06F1/26 ; G06F1/30 ; G06F15/78 ; G11C11/4074 ; G11C11/412 ; G11C11/413 ; G11C11/417 ; G11C11/40
摘要:
A RAM being powered by a standby voltage supply and having control circuitry to save all or a portion of the information stored in the RAM during power up and power down is provided. A latch is used to hold an input signal just prior to power down to just after power up. The latch is coupled to read and write and word select logic so that the latch can inhibit the read and write logic as well as inhibiting the addressability of any storage cells in the retained portion of the RAM during power up and power down. Transistors having a control electrode are connected to the word select lines of the RAM and hold the word select lines near zero voltage during power up and power down to prevent information from flowing on the word select lines. The control electrodes of the transistors are connected to an output of the latch.
公开/授权文献
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