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公开(公告)号：US4314353A
公开(公告)日：1982-02-02
申请号：US884947
申请日：1978-03-09
CPC分类号： G06F15/786 , G06F13/4022
摘要： A microprocessor interconnected to a RAM on the same integrated circuit chip. Interconnect circuitry connects the RAM to the microprocessor data bus to allow RAM data to be transferred to an instruction register of the microprocessor which permits the RAM to contain instructions and operation codes. A sense amplifier is used to provide an output from the RAM. At least one buffer is coupled to the output of the sense amplifier. A bilateral switch is coupled to the at least one buffer and controllably switches the output of the at least one buffer to the microprocessor internal data bus and to an external data bus.
摘要翻译： 与同一集成电路芯片上的RAM互连的微处理器。 互连电路将RAM连接到微处理器数据总线，以允许RAM数据传输到微处理器的指令寄存器，这允许RAM包含指令和操作代码。 读出放大器用于提供RAM的输出。 至少一个缓冲器耦合到读出放大器的输出端。 双向开关耦合到至少一个缓冲器，并且可控制地将至少一个缓冲器的输出切换到微处理器内部数据总线和外部数据总线。
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公开(公告)号：US4296469A
公开(公告)日：1981-10-20
申请号：US961798
申请日：1978-11-17
CPC分类号： G06F15/7832 , G06F9/38
摘要： A data processor having an execution unit employs a segmented bus structure and a dual port register cell in order to increase circuit density and in order to allow address and data computations to occur simultaneously. The circuit is designed to interface with an external 16-bit bidirectional data bus and an external address bus having as many as 32 address bits. Serial bus switches on each of two parallel buses allow concatenation with a second pair of buses. Each bus, while 16 bits wide, actually utilizes two conductors per bit to carry data and the complement thereof.
摘要翻译： 具有执行单元的数据处理器采用分段总线结构和双端口寄存器单元，以便增加电路密度并且允许地址和数据计算同时发生。 该电路设计为与外部16位双向数据总线和具有多达32个地址位的外部地址总线进行接口。 两个并行总线中的每个串行总线开关允许与第二对总线连接。 每个总线，而16位宽，实际上每位使用两个导体来承载数据及其补码。
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公开(公告)号：US4349873A
公开(公告)日：1982-09-14
申请号：US136593
申请日：1980-04-02
CPC分类号： G06F9/4812 , G06F11/0721 , G06F11/0745 , G06F11/0751 , G06F11/0757
摘要： An integrated circuit data processor receives interrupt level signals from external circuitry which represent a priority level associated with the external circuitry. These signals are compared with signals representing the current operating level of the processor, and an interrupt pending output is generated if (1) the priority level is higher than the operating level; or (2) a maximum priority level is received. Upon the occurrence of the interrupt pending output, the current instruction program is interrupted, and an instruction program associated with the external circuitry is executed. The processor transmits a signal back to the external circuitry indicating that the interrupt request has been granted and receives a vector number from the external circuitry. A first acknowledgment signal from the external circuitry causes the vector number to be latched in the processor. A second acknowledgment signal from the external circuitry causes a vector to be internally generated. Error circuitry is provided to detect spurious interrupts.
摘要翻译： 集成电路数据处理器从外部电路接收表示与外部电路相关联的优先级的中断电平信号。 将这些信号与表示处理器的当前操作电平的信号进行比较，并且如果（1）优先级高于操作电平，则产生中断等待输出; 或（2）接收到最大优先级。 当发生中断等待输出时，当前指令程序中断，并且执行与外部电路相关联的指令程序。 处理器向外部电路发送一个信号，指示中断请求已被授权，并从外部电路接收一个向量号。 来自外部电路的第一确认信号使得矢量编号被锁存在处理器中。 来自外部电路的第二确认信号导致向量在内部产生。 提供错误电路来检测虚假中断。
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公开(公告)号：US4338661A
公开(公告)日：1982-07-06
申请号：US41201
申请日：1979-05-21
摘要： A data processor having a microprogrammed control store and including a conditional branch control unit for receiving selection bits output by the control store, selection bits from an instruction register, and conditional signals for generating a two-bit result which, when added to a base address, can specify one of two, three, or four branch destinations in the control store. The selection bits output by the control store determine whether the combination of conditional signals upon which the branch is dependent is selected by the control store or is selected directly by a bit field in the macroinstruction. Also, one of the selection bits output by the control store is used to select one of two possible output codes for the two-bit result associated with a particular branch destination. The latter feature allows for two conditional branch points in the control store to test for the same condition and to select the same destination when the tested condition is of one logic state while selecting different destinations when the tested condition is of the opposite logic state.
摘要翻译： 具有微程序控制存储的数据处理器，包括用于接收由控制存储器输出的选择位的条件转移控制单元，来自指令寄存器的选择位，以及用于产生两位结果的条件信号，当加到基址 ，可以在控制存储中指定两个，三个或四个分支目的地之一。 由控制存储器输出的选择位决定是否由控制存储器选择分支所依赖的条件信号的组合，或由宏指令中的位字段直接选择。 而且，由控制存储器输出的选择位之一用于选择与特定分支目的地相关联的两位结果的两个可能输出代码之一。 后一个特征允许控制存储器中的两个条件分支点测试相同的条件，并且当测试条件是一个逻辑状态时选择相同的目的地，而当测试条件是相反的逻辑状态时，选择不同的目的地。
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公开(公告)号：US4312034A
公开(公告)日：1982-01-19
申请号：US41203
申请日：1979-05-21
CPC分类号： G06F9/30094 , G06F9/262 , G06F9/30145 , G06F9/30167
摘要： A data processor which is adapted for microprogrammed operation has a control store includes an ALU and condition code control unit for controlling operations performed by an arithmetic-logic unit within the execution unit of the data processor and for controlling the setting of the condition code bits in a status register. The ALU and condition code control unit is arranged in a row and column format. A decoder coupled to a macroinstruction register selects a row which is selected over an entire period that is required to execute macroinstruction. The row corresponds to a set of operations and condition code settings associated with a particular macroinstruction. The control store output provides information for selecting the proper column during each microcycle used to execute the macroinstruction. ALU function control signals and the condition code control signals are selected simultaneously according to the selected row and column.
摘要翻译： 适用于微程序操作的数据处理器具有控制存储器，其包括ALU和条件代码控制单元，用于控制由数据处理器的执行单元内的算术逻辑单元执行的操作，并用于控制数据处理器中的条件码位的设置 状态寄存器。 ALU和条件代码控制单元以行和列格式排列。 耦合到宏指令寄存器的解码器选择在执行宏指令所需的整个周期中选择的行。 该行对应于与特定宏指令相关联的一组操作和条件代码设置。 控制存储输出提供用于在用于执行宏指令的每个微循环期间选择适当列的信息。 ALU功能控制信号和条件代码控制信号根据所选行和列同时选择。
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公开(公告)号：US4145761A
公开(公告)日：1979-03-20
申请号：US884790
申请日：1978-03-09
申请人： Thomas G. Gunter , Fuad H. Musa , Pern Shaw , Michael F. Wiles
发明人： Thomas G. Gunter , Fuad H. Musa , Pern Shaw , Michael F. Wiles
IPC分类号： G06F12/16 , G06F1/26 , G06F1/30 , G06F15/78 , G11C11/4074 , G11C11/412 , G11C11/413 , G11C11/417 , G11C11/40
CPC分类号： G11C11/417 , G06F1/30 , G11C11/4074 , G11C11/412
摘要： A RAM being powered by a standby voltage supply and having control circuitry to save all or a portion of the information stored in the RAM during power up and power down is provided. A latch is used to hold an input signal just prior to power down to just after power up. The latch is coupled to read and write and word select logic so that the latch can inhibit the read and write logic as well as inhibiting the addressability of any storage cells in the retained portion of the RAM during power up and power down. Transistors having a control electrode are connected to the word select lines of the RAM and hold the word select lines near zero voltage during power up and power down to prevent information from flowing on the word select lines. The control electrodes of the transistors are connected to an output of the latch.
摘要翻译： 提供由备用电源供电并具有控制电路的RAM，以在上电和断电期间保存存储在RAM中的全部或一部分信息。 锁存器用于在掉电之前刚刚上电后保持输入信号。 锁存器耦合到读和写选择逻辑，使得锁存器可以禁止读和写逻辑，以及在上电和掉电期间禁止RAM的保留部分中的任何存储单元的寻址能力。 具有控制电极的晶体管连接到RAM的字选择线，并且在加电和掉电期间将字选择线保持在零电压附近，以防止信息在字选择线上流动。 晶体管的控制电极连接到锁存器的输出端。
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公开(公告)号：US4348741A
公开(公告)日：1982-09-07
申请号：US169558
申请日：1980-07-17
CPC分类号： G06F7/74 , G06F9/30043 , H03M11/02
摘要： Each channel of a priority encoder register is equipped with a latch for storing one bit of a binary data word. The channel of highest priority generates an output which is applied to encoding means which in turn generates a unique code. The channel output is also fed back to reset its associated latch to permit the channel of next highest priority to generate an output.
摘要翻译： 优先编码器寄存器的每个通道配备有用于存储二进制数据字的一位的锁存器。 最高优先级的信道产生应用于编码装置的输出，该编码装置又产生唯一的码。 信道输出也被反馈以复位其相关联的锁存器，以允许下一个最高优先级的信道生成输出。
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公开(公告)号：US4325121A
公开(公告)日：1982-04-13
申请号：US41135
申请日：1979-05-21
CPC分类号： G06F9/26
摘要： A data processor having an execution unit and which includes a control means having a first and a second control store. The control means has an input for receiving a control store address. In response to the received control store address, the first control store provides sequencing information at a first output for selecting the next control store address. Also, in response to the received control store address, the second control store supplies control information at a second output for controlling the execution unit. The data processor also includes means for receiving a macroinstruction and selection means responsive to the macroinstruction and to the sequencing information for generating the control store address. In a preferred embodiment, the control store address is received by both the input of the first control store and the input of the second control store. Each control word in the first control store has a unique control store address. However, a control word, in the second control store may be selected by many different control store addresses.
摘要翻译： 一种具有执行单元并且包括具有第一和第二控制存储器的控制装置的数据处理器。 控制装置具有用于接收控制存储地址的输入。 响应于所接收的控制存储地址，第一控制存储器在第一输出端提供排序信息，用于选择下一个控制存储地址。 此外，响应于接收的控制存储地址，第二控制存储器在用于控制执行单元的第二输出端提供控制信息。 数据处理器还包括用于接收响应于宏指令的宏指令和选择装置以及用于生成控制存储器地址的排序信息的装置。 在优选实施例中，控制存储地址由第一控制存储器的输入和第二控制存储器的输入两者接收。 第一控制存储器中的每个控制字具有唯一的控制存储地址。 然而，可以通过许多不同的控制存储地址来选择第二控制存储器中的控制字。
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9.发明授权Microprogrammed control apparatus having a two-level control store for data processor 失效具有用于数据处理器的两级控制存储器的微编程控制装置
公开(公告)号：US4307445A
公开(公告)日：1981-12-22
申请号：US961796
申请日：1978-11-17
CPC分类号： G06F9/26
摘要： A microprogrammed control structure for an integrated circuit data processor which employs a two-level control store designated as a micro control store and nano control store. An instruction decoder decodes each macro instruction to be executed by the data processor and causes a series of micro word addresses to be input to the micro control store. In response to such input, the micro control store outputs a corresponding number of nano address words for addressing the nano control store. The nano control store when addressed by the nano address words, outputs a control word to an execution unit for executing the macro instruction.
摘要翻译： 一种用于集成电路数据处理器的微程序控制结构，其采用被指定为微控制存储器和纳米控制存储器的两级控制存储器。 指令译码器对由数据处理器执行的每个宏指令进行解码，并将一系列微字地址输入微控制存储器。 响应于这样的输入，微控制器输出相应数量的纳米地址字用于寻址纳米控制存储器。 当由纳米地址字寻址时，纳米控制存储器将控制字输出到用于执行宏指令的执行单元。
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公开(公告)号：US4348722A
公开(公告)日：1982-09-07
申请号：US136845
申请日：1980-04-03
CPC分类号： G06F11/141
摘要： An integrated circuit microprocessor includes storage means coupled to a control unit for receiving from the control unit information regarding how the next bus cycle is to be run. Upon receipt of a bus error signal from a peripheral device, the storage means is reset. If, however, a halt signal accompanies the bus error signal, the storage means is not reset and the bus cycle is rerun when the halt signal terminates.
摘要翻译： 集成电路微处理器包括耦合到控制单元的存储装置，用于从控制单元接收关于如何运行下一个总线周期的信息。 在从外围设备接收到总线错误信号时，存储装置被复位。 然而，如果停止信号伴随总线误差信号，则存储装置不复位，并且当停止信号终止时总线周期重新运行。
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