公开(公告)号：US4432049A

公开(公告)日：1984-02-14

申请号：US192157

申请日：1980-09-29

申请人： Pern Shaw ,  Donald L. Tietjen ,  Michael F. Wiles

发明人： Pern Shaw ,  Donald L. Tietjen ,  Michael F. Wiles

IPC分类号： G06F1/00 ,  G06F3/00 ,  H03K17/00

CPC分类号： G06F1/00

摘要： A mode selection circuit is disclosed which is suitable for configuring a data processor at the time at which the data processor is initialized with a reset signal. Mode selection latches are coupled to terminals normally used as an input/output port for the data processor and the latches are clocked with a signal generated by a level detector circuit which senses the reset signal. The mode selection latches are programmed by applying appropriate logic levels to the terminals of the input/output port at the time at which the data processor is being reset. The circuitry is adapted for allowing the connection of a diode from a terminal of the input/output port to the reset terminal of the data processor in order to program a low logic level into the corresponding mode detection latch.

摘要翻译： 公开了一种模式选择电路，其适于在数据处理器用复位信号初始化时配置数据处理器。 模式选择锁存器耦合到通常用作数据处理器的输入/输出端口的端子，并且锁存器由检测复位信号的电平检测器电路产生的信号计时。 通过在数据处理器被复位时对输入/输出端口的端子应用适当的逻辑电平来对模式选择锁存器进行编程。 电路适于允许将二极管从输入/输出端口的端子连接到数据处理器的复位端，以将低逻辑电平编程到相应的模式检测锁存器中。

公开(公告)号：US4329656A

公开(公告)日：1982-05-11

申请号：US82458

申请日：1979-10-09

申请人： Pern Shaw

发明人： Pern Shaw

IPC分类号： H03F3/45 ,  H03M1/00

CPC分类号： H03F3/45071 ,  H03M1/361

摘要： A subtractor for use in a digital to digital converter has fast response and uses an operational amplifier. The fast response is achieved by varying current flow in associated circuits. An analog input controls current flow through a first portion of the circuitry and a voltage reference controls current flow through a second portion of the circuit. The total current flow through the first and second portions of the circuit is provided by a current source. The analog input is coupled to a first input of the operational amplifier and the voltage reference is coupled to a second input of the operational amplifier. A first logarithmic impedance is coupled between the first input of the operational amplifier and the output of the operational amplifier. A second logarithmic impedance is coupled between the second input of the operational amplifier and a bias voltage. The bias voltage is used to provide a predetermined biased voltage at the output of the operational amplifier.

摘要翻译： 用于数模转换器的减法器具有快速响应并使用运算放大器。 通过改变相关电路中的电流来实现快速响应。 模拟输入控制通过电路的第一部分的电流，并且电压基准控制通过电路的第二部分的电流。 流过电路的第一和第二部分的总电流通过电流源提供。 模拟输入耦合到运算放大器的第一输入，并且电压基准耦合到运算放大器的第二输入端。 第一对数阻抗耦合在运算放大器的第一输入端和运算放大器的输出端之间。 第二对数阻抗耦合在运算放大器的第二输入端和偏置电压之间。 偏置电压用于在运算放大器的输出处提供预定的偏置电压。

公开(公告)号：US4317053A

公开(公告)日：1982-02-23

申请号：US100785

申请日：1979-12-05

申请人： Pern Shaw ,  Stanley E. Groves

发明人： Pern Shaw ,  Stanley E. Groves

IPC分类号： H03K5/135 ,  H03K19/08 ,  H03K1/17

CPC分类号： H03K5/135

摘要： In a high speed synchronizing circuit, the rising edge of an asynchronous input signal is used to set an input RS flip-flop. First and second latch registers monitor the input RS flip-flop. Each latch register generates a reset signal before a change in the logic level of the system clock for resetting the input RS flip-flop. The reset pulses are very narrow which enables the RS flip-flop to be quickly conditioned to receive the next asynchronous signal.

摘要翻译： 在高速同步电路中，异步输入信号的上升沿用于设置输入RS触发器。 第一和第二锁存寄存器监视输入RS触发器。 在用于复位输入RS触发器的系统时钟的逻辑电平变化之前，每个锁存寄存器产生一个复位信号。 复位脉冲非常窄，这使得RS触发器能够被快速调节以接收下一个异步信号。

公开(公告)号：US4224539A

公开(公告)日：1980-09-23

申请号：US939725

申请日：1978-09-05

申请人： Fuad H. Musa ,  Pern Shaw

发明人： Fuad H. Musa ,  Pern Shaw

IPC分类号： G01R19/165 ,  G05F3/24 ,  H03K5/20 ,  H03K1/12 ,  H03K17/30

CPC分类号： G05F3/247 ,  G01R19/16519

摘要： There is provided a voltage level detecting circuit useful as power-up/power-down voltage indicator for a field effect transistor integrated circuit. A constant voltage reference generator is provided by a depletion type transistor in series with two enhancement type transistors coupled between power supply terminals of the integrated circuit chip. Each of the enhancement type transistors have their gate electrodes connected to their drain electrodes while the depletion type transistor has its gate electrode connected to the more negative or reference terminal of the power supply voltage. A constant voltage output is taken from between the junction of one of the enhancement mode transistors and the depletion type transistor. This constant voltage output can be compared against a voltage obtained from a voltage divider circuit which provides an output that varies in accordance with variations in the power supply. The voltage level detector circuit is particularly useful in microprocessors and microcomputer integrated circuit chips.

摘要翻译： 提供了用作场效应晶体管集成电路的用于上电/掉电电压指示器的电压电平检测电路。 恒定电压基准发生器由与集成电路芯片的电源端子耦合的两个增强型晶体管串联的耗尽型晶体管提供。 每个增强型晶体管的栅电极连接到它们的漏极，而耗尽型晶体管的栅电极连接到电源电压的更负的或参考端。 从增强型晶体管之一和耗尽型晶体管的结之间取出恒定电压输出。 该恒定电压输出可以与提供根据电源的变化而变化的输出的分压器电路获得的电压进行比较。 电压电平检测器电路在微处理器和微计算机集成电路芯片中特别有用。

公开(公告)号：US4918333A

公开(公告)日：1990-04-17

申请号：US264733

申请日：1988-10-31

申请人： Floyd E. Anderson ,  Stephen P. Robb ,  Pern Shaw ,  Lewis E. Terry

发明人： Floyd E. Anderson ,  Stephen P. Robb ,  Pern Shaw ,  Lewis E. Terry

IPC分类号： G06F15/78 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H03K17/06

CPC分类号： H01L27/0207 ,  H03K17/063 ,  H01L27/0203

摘要： An integrated circuit having a microprocessor core interfaced to large power transistors is described. This integrated circuit provides the capability to intelligently control and drive loads requiring currents exceeding 250 milli amps. The large power transistors are built in a technology compatible with the microprocessor core technology resulting in a more readily manufacturable circuit. The microprocessor core is layed out in a manner which provides the greatest distance between the most heat sensitive microprocessor core circuits and the power devices. On chip temperature sensing and feedback is provided for junction temperature monitoring and control.

公开(公告)号：US4349870A

公开(公告)日：1982-09-14

申请号：US72739

申请日：1979-09-05

申请人： Pern Shaw ,  Fuad H. Musa

发明人： Pern Shaw ,  Fuad H. Musa

IPC分类号： G06F13/36 ,  G06F15/78 ,  G06F3/00

CPC分类号： G06F13/36 ,  G06F15/7814

摘要： A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), four I/O ports (11-14) and various power supply, clock, and control inputs. One of the I/O ports (13) is user programmable by application of specific signals to mode selection pins (P20-22) for configuration in several possible ways. The programmable port comprises a plurality of lines which each may be individually programmed as input or output lines to peripheral equipment associated with the microcomputer. Alternatively, the port lines can be programmed to serve as a bidirectional data bus to external memory. Alternatively, the port lines can be programmed to be multiplexed data and address lines to external memory. Bus arbitration logic is provided to route data to the CPU from either on-chip memory or external memory.

摘要翻译： 单片机包括CPU（1），RAM（2），ROM（3），定时器（4），串行I / O通信逻辑（5），四个I / O端口（11-14） 和各种电源，时钟和控制输入。 其中一个I / O端口（13）可以通过将特定信号应用于模式选择引脚（P20-22）进行用户编程，以便以多种可能的方式进行配置。 可编程端口包括多条线路，每条线路可以单独编程为与微计算机相关联的外围设备的输入或输出线路。 或者，端口线可以被编程为用作到外部存储器的双向数据总线。 或者，端口线可以被编程为多路复用数据和地址线到外部存储器。 提供总线仲裁逻辑以将数据从片上存储器或外部存储器路由到CPU。

公开(公告)号：US4214233A

公开(公告)日：1980-07-22

申请号：US807472

申请日：1977-06-17

申请人： Pern Shaw ,  Fuad H. Musa ,  Stephen J. Kreinick

发明人： Pern Shaw ,  Fuad H. Musa ,  Stephen J. Kreinick

IPC分类号： H03M1/00 ,  H03K13/175

CPC分类号： H03M1/1019 ,  H03M1/682

摘要： An analog-to-digital converter includes a first and a second comparator each of which receives an analog input. The first comparator generates a plurality of reference voltages which establish a first continuous range of voltage gaps. The first comparator has a plurality of quantizing outputs, one of which will be at a logical one and the rest of which will be at logical zeros in order to indicate which of the voltage gaps encompasses the analog input voltage. The first comparator also has first and second reference current outputs whose magnitudes are representative of which voltage gap encompasses the analog input voltage and a third reference current output whose magnitude is representative of the voltage gap width. A first encoder receives the quantizing outputs of the first comparator and generates a binary number which represents which of the voltage gaps the analog input voltage is encompassed by and which constitutes the most significant bit group of the binary digital representation of the analog input voltage. The reference current outputs of the first comparator are input to a reference voltage level shifting circuit whose output voltage represents the voltage difference between a first boundary of the voltage gap which encompasses the analog input voltage and the maximum reference voltage value associated with the first comparator. The reference voltage level shifting output voltage is produced concurrently with the action of the first encoder, thereby providing overlapping operations for increased conversion speeds. This shifted reference voltage is provided as an input to a second comparator which compares the analog input with a plurality of internal reference voltages which form a second continuous range of voltage gaps. The second comparator has a plurality of outputs, one corresponding to each of the voltage gaps encompassed by the reference voltages in the second comparator. The second comparator produces a logical one on an output corresponding to the particular voltage gap defined by the shifted reference voltage. A second encoder receives as inputs the outputs of the second comparator and generates a binary output which represents the least significant bit group of the analog input voltage. In combination, the output of the first encoder and the output of the second encoder form a binary digital representation of the analog input voltage, including the most significant bits and the least significant bits thereof.

公开(公告)号：US4924112A

公开(公告)日：1990-05-08

申请号：US264732

申请日：1988-10-31

申请人： Floyd E. Anderson ,  Stephen P. Robb ,  Pern Shaw

发明人： Floyd E. Anderson ,  Stephen P. Robb ,  Pern Shaw

IPC分类号： H03K17/08 ,  H03K17/082

CPC分类号： H03K17/0826 ,  H03K17/0822 ,  H03K2017/0806

摘要： An integrated circuit having a microprocessor core interfaced to large power transistors is described. This integrated circuit provides the capability to intelligently control and drive loads requiring currents exceeding 250 milli amps. The large power transistors are built in a technology compatible with the microprocessor core technology resulting in a more readily manufacturable circuit. The microprocessor core is layed out in a manner which provides the greatest distance between the most heat sensitive microprocessor core circuits and the power devices. On chip temperature sensing and feedback is provided for junction temperature monitoring and control.

摘要翻译： 描述了具有与大功率晶体管连接的微处理器核心的集成电路。 该集成电路提供智能控制和驱动需要电流超过250毫安的负载的能力。 大功率晶体管内置于与微处理器核心技术相兼容的技术，从而形成更容易制造的电路。 微处理器内核以最热敏微处理器核心电路和功率器件之间提供最大距离的方式布置。 提供片上温度检测和反馈，用于结温监测和控制。

公开(公告)号：US4218675A

公开(公告)日：1980-08-19

申请号：US807470

申请日：1977-06-17

申请人： Pern Shaw ,  Fuad H. Musa ,  Stephen J. Kreinick

发明人： Pern Shaw ,  Fuad H. Musa ,  Stephen J. Kreinick

IPC分类号： H03M1/00 ,  H03K13/175

CPC分类号： H03M1/447

摘要： An analog-to-digital converter includes a first and a second comparator. The first comparator generates a plurality of quantizing outputs defining voltage gaps and also has first and second reference current outputs whose magnitudes are representative of which voltage gap encompasses the analog input voltage and a third reference current output whose magnitude is representative of the voltage gap width. A first encoder receives the quantizing outputs of the first comparator and generates a binary number which represents which of the voltage gaps the analog input voltage is encompassed by. The reference current outputs of the first comparator are input to a reference voltage level shifting circuit whose shifted reference output voltage is provided as an input to a second comparator which compares the analog input with a plurality of internal reference voltages which form a second continuous range of voltage gaps. The second comparator has a plurality of outputs, one corresponding to each of the voltage gaps encompassed by the reference voltages in the second comparator. A second encoder receives as inputs the outputs of the second comparator and generates a binary output which represents the least significant bit group of the analog input voltage.

摘要翻译： 模数转换器包括第一和第二比较器。 第一比较器产生限定电压间隙的多个量化输出，并且还具有第一和第二参考电流输出，其大小代表哪个电压间隙包围模拟输入电压，以及第三参考电流输出，其大小代表电压间隙宽度。 第一编码器接收第一比较器的量化输出并产生二进制数，该二进制数表示模拟输入电压被包围的电压间隙中的哪一个。 第一比较器的参考电流输出被输入到参考电压电平移位电路，其移位的基准输出电压作为输入被提供给第二比较器，该第二比较器将模拟输入与形成第二连续范围的多个内部参考电压进行比较 电压差。 第二比较器具有多个输出，一个对应于由第二比较器中的参考电压包围的每个电压间隙。 第二编码器接收第二比较器的输出作为输入，并产生表示模拟输入电压的最低有效位组的二进制输出。

公开(公告)号：US4145761A

公开(公告)日：1979-03-20

申请号：US884790

申请日：1978-03-09

申请人： Thomas G. Gunter ,  Fuad H. Musa ,  Pern Shaw ,  Michael F. Wiles

发明人： Thomas G. Gunter ,  Fuad H. Musa ,  Pern Shaw ,  Michael F. Wiles

IPC分类号： G06F12/16 ,  G06F1/26 ,  G06F1/30 ,  G06F15/78 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C11/40

CPC分类号： G11C11/417 ,  G06F1/30 ,  G11C11/4074 ,  G11C11/412

摘要： A RAM being powered by a standby voltage supply and having control circuitry to save all or a portion of the information stored in the RAM during power up and power down is provided. A latch is used to hold an input signal just prior to power down to just after power up. The latch is coupled to read and write and word select logic so that the latch can inhibit the read and write logic as well as inhibiting the addressability of any storage cells in the retained portion of the RAM during power up and power down. Transistors having a control electrode are connected to the word select lines of the RAM and hold the word select lines near zero voltage during power up and power down to prevent information from flowing on the word select lines. The control electrodes of the transistors are connected to an output of the latch.

摘要翻译： 提供由备用电源供电并具有控制电路的RAM，以在上电和断电期间保存存储在RAM中的全部或一部分信息。 锁存器用于在掉电之前刚刚上电后保持输入信号。 锁存器耦合到读和写选择逻辑，使得锁存器可以禁止读和写逻辑，以及在上电和掉电期间禁止RAM的保留部分中的任何存储单元的寻址能力。 具有控制电极的晶体管连接到RAM的字选择线，并且在加电和掉电期间将字选择线保持在零电压附近，以防止信息在字选择线上流动。 晶体管的控制电极连接到锁存器的输出端。