发明授权
- 专利标题: Method of manufacturing intergrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
- 专利标题(中): 使用自对准双扩散技术制造集成注入逻辑半导体器件的方法
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申请号: US822194申请日: 1977-08-05
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公开(公告)号: US4153487A公开(公告)日: 1979-05-08
- 发明人: Yukuya Tokumaru , Masanori Nakai , Satoshi Shinozaki , Junichi Nakamura , Shintaro Ito , Yoshio Nishi
- 申请人: Yukuya Tokumaru , Masanori Nakai , Satoshi Shinozaki , Junichi Nakamura , Shintaro Ito , Yoshio Nishi
- 申请人地址: JPX
- 专利权人: Tokyo Shibaura Electric Co., Ltd.
- 当前专利权人: Tokyo Shibaura Electric Co., Ltd.
- 当前专利权人地址: JPX
- 优先权: JPX49/148795 19741227; JPX49/148796 19741227; JPX49/148797 19741227; JPX49/1913 19741227
- 主分类号: H01L21/033
- IPC分类号: H01L21/033 ; H01L21/8226 ; H01L27/02 ; H01L21/22 ; H01L21/76 ; H01L27/04
摘要:
A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.
公开/授权文献
- US5892178A Support fixture for control panel assembly 公开/授权日:1999-04-06
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