公开(公告)号：US4459606A

公开(公告)日：1984-07-10

申请号：US644296

申请日：1975-12-24

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L29/73 ,  H01L27/04 ,  H03K19/091

CPC分类号： H01L27/0214

摘要： The integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on the N type semiconductor substrate, a first N type region extending through the P type semiconductor layer to reach the N type semiconductor substrate, a P type region formed in the first N type region and having a periphery along the outer periphery of the first N type region and a second N type region formed in the P type semiconductor layer. The integrated injection logic semiconductor device is constituted by a PNP lateral transistor utilizing the P type region, the first N type region and the P type semiconductor layer as the emitter, base and collector electrodes respectively, and a NPN vertical transistor utilizing the N type semiconductor substrate, P type semiconductor layer and the second N type region as the emitter, base and collector electrodes, respectively.

摘要翻译： 集成注入逻辑半导体器件包括N型半导体衬底，层叠在N型半导体衬底上的P型半导体层，延伸穿过P型半导体层到达N型半导体衬底的第一N型区域，P型区域 形成在第一N型区域中，并且沿着第一N型区域的外周具有周边，以及形成在P型半导体层中的第二N型区域。 集成注入逻辑半导体器件分别由利用P型区域，第一N型区域和P型半导体层作为发射极，基极和集电极的PNP横向晶体管构成，以及利用N型半导体的NPN垂直晶体管 基板，P型半导体层和第二N型区域分别作为发射极，基极和集电极。

公开(公告)号：US4058419A

公开(公告)日：1977-11-15

申请号：US644294

申请日：1975-12-24

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L21/033 ,  H01L21/8226 ,  H01L27/02 ,  H01L21/22 ,  H01L21/76 ,  H01L27/04

CPC分类号： H01L21/8226 ,  H01L21/033 ,  H01L27/0233

摘要： A P type semiconductor layer is formed on an N type semiconductor layer by vapour epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.

摘要翻译： 通过蒸气外延生长技术在N型半导体层上形成P型半导体层，在P型半导体层上形成绝缘膜，通过绝缘膜设置栅格状的第一开口。 然后，磷通过栅格形状开口扩散到P型半导体层中，以形成延伸穿过半导体层的第一N型区域到达N型半导体层。 然后，通过由栅格形状的第一开口分隔并被其包围的绝缘膜的各个部分形成第二开口，并且硼通过第一和第二开口扩散，以形成网格形状的第一N型区域中的第一和第二P型区域， P型半导体层。 最后，通过绝缘膜的各部分形成第三开口，并且磷通过第三开口扩散到P型半导体层中，以形成第二N型区域，从而形成包括横向PNP晶体管和垂直NPN的集成注入逻辑半导体器件 晶体管。

公开(公告)号：US4153487A

公开(公告)日：1979-05-08

申请号：US822194

申请日：1977-08-05

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L21/033 ,  H01L21/8226 ,  H01L27/02 ,  H01L21/22 ,  H01L21/76 ,  H01L27/04

CPC分类号： H01L21/8226 ,  H01L21/033 ,  H01L27/0233

摘要： A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.

摘要翻译： 通过蒸气外延生长技术在N型半导体层上形成P型半导体层，在P型半导体层上形成绝缘膜，通过绝缘膜设置栅格状的第一开口。 然后，磷通过栅格形状开口扩散到P型半导体层中，以形成延伸穿过半导体层的第一N型区域到达N型半导体层。 然后，通过由栅格形状的第一开口分隔并被其包围的绝缘膜的各个部分形成第二开口，并且硼通过第一和第二开口扩散，以形成网格形状的第一N型区域中的第一和第二P型区域， P型半导体层。 最后，通过绝缘膜的各部分形成第三开口，并且磷通过第三开口扩散到P型半导体层中，以形成第二N型区域，从而形成包括横向PNP晶体管和垂直NPN的集成注入逻辑半导体器件 晶体管。

公开(公告)号：US4151019A

公开(公告)日：1979-04-24

申请号：US822322

申请日：1977-08-05

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L21/033 ,  H01L21/8226 ,  H01L27/02 ,  H01L21/22 ,  H01L21/76 ,  H01L27/04

CPC分类号： H01L21/033 ,  H01L21/8226 ,  H01L27/0233

摘要： A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.

摘要翻译： 通过蒸气外延生长技术在N型半导体层上形成P型半导体层，在P型半导体层上形成绝缘膜，通过绝缘膜设置栅格状的第一开口。 然后，磷通过栅格形状开口扩散到P型半导体层中，以形成延伸穿过半导体层的第一N型区域到达N型半导体层。 然后，通过由栅格形状的第一开口分隔并被其包围的绝缘膜的各个部分形成第二开口，并且硼通过第一和第二开口扩散，以形成网格形状的第一N型区域中的第一和第二P型区域， P型半导体层。 最后，通过绝缘膜的各部分形成第三开口，并且磷通过第三开口扩散到P型半导体层中，以形成第二N型区域，从而形成包括横向PNP晶体管和垂直NPN的集成注入逻辑半导体器件 晶体管。

公开(公告)号：US4119998A

公开(公告)日：1978-10-10

申请号：US815768

申请日：1977-07-14

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L27/02 ,  H01L27/04

CPC分类号： H01L27/0233

摘要： An integrated injection logic semiconductor device is composed of an N type semiconductor substrate, a P type layer, a first N type region so formed as to penetrate through the P type semiconductor layer and contact the N type semiconductor substrate, a second N type region formed in the P type semiconductor layer, and a P type region formed in the first N type region. A third N type region is provided surrounding said first and second N type regions and penetrating through the P type semiconductor layer. I.sup.2 L circuit is composed of a lateral PNP transistor whose emitter, base and collector are constituted by said P type region, said first N type region and said P type semiconductor layer, respectively, and a vertical NPN transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, said P type semiconductor layer and said second N type region, respectively.

摘要翻译： 集成注入逻辑半导体器件由N型半导体衬底，P型层，形成为穿透P型半导体层并接触N型半导体衬底的第一N型区域构成，形成第二N型区域 在P型半导体层中形成的P型区域和形成在第一N型区域中的P型区域。 围绕所述第一和第二N型区域并穿过P型半导体层设置第三N型区域。 I2L电路由发射极，基极和集电极分别由所述P型区域，所述第一N型区域和所述P型半导体层分别构成的横向PNP晶体管和其发射极，基极和集电极构成的垂直NPN晶体管构成 分别由所述N型半导体衬底，所述P型半导体层和所述第二N型区域。

公开(公告)号：US4064526A

公开(公告)日：1977-12-20

申请号：US644048

申请日：1975-12-24

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L29/73 ,  H01L27/04 ,  H01L29/36 ,  H01L29/72

CPC分类号： H01L27/0237 ,  Y10S148/085 ,  Y10S148/087 ,  Y10S148/167

摘要： An integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on said semiconductor substrate, and N type first region formed in a manner penetrating through said P type semiconductor layer to reach said N type semiconductor substrate, a first P type region formed in said first N type region, a second N type regionformed in said P type semiconductor layer, and a second P type region formed between said second N type region and said N type semiconductor substrate in a manner connected directly to said N type semiconductor substrate. An integrated injection logic circuit is comprised of a lateral NPN transistor whose emitter, base and collector are constituted by said first P type region, first N type region and P type semiconductor layer, respectively, and a vertical PNP transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, P type semiconductor layer plus second P type region, and second N type region, respectively.

摘要翻译： 一种集成注入逻辑半导体器件，包括N型半导体衬底，层叠在所述半导体衬底上的P型半导体层和以穿过所述P型半导体层的方式形成以到达所述N型半导体衬底的N型第一区域，第一 形成在所述第一N型区域中的P型区域，形成在所述P型半导体层中的第二N型区域和形成在所述第二N型区域和所述N型半导体衬底之间的第二P型区域， 型半导体衬底。 集成注入逻辑电路由横向NPN晶体管组成，其发射极，基极和集电极分别由所述第一P型区域，第一N型区域和P型半导体层构成，垂直PNP晶体管的发射极，基极和集电极 分别由所述N型半导体衬底，P型半导体层加上第二P型区域和第二N型区域构成。

公开(公告)号：US4054900A

公开(公告)日：1977-10-18

申请号：US644293

申请日：1975-12-24

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L27/02 ,  H01L29/72 ,  H01L27/04 ,  H03K19/08

CPC分类号： H01L27/0233

摘要： An integrated injection logic semiconductor device which comprises an N type semiconductor substrate; a P type semiconductor layer superposed on the N type semiconductor substrate; a first N type region formed in the P type semiconductor layer; a second N type region formed in the P type semiconductor layer; and a P type region formed in the first N type region, wherein the first N type region is connected to the N type semiconductor substrate through an N type connector region formed between the first N type region and N type semiconductor substrate.

摘要翻译： 一种包括N型半导体衬底的集成注入逻辑半导体器件; 叠置在N型半导体衬底上的P型半导体层; 形成在P型半导体层中的第一N型区域; 形成在P型半导体层中的第二N型区域; 以及形成在所述第一N型区域中的P型区域，其中所述第一N型区域通过形成在所述第一N型区域和N型半导体衬底之间的N型连接器区域与所述N型半导体衬底连接。

公开(公告)号：US4172384A

公开(公告)日：1979-10-30

申请号：US909303

申请日：1978-05-24

申请人： Hiroshi Tamura ,  Masao Kato ,  Yukuya Tokumaru ,  Masanori Nakai

发明人： Hiroshi Tamura ,  Masao Kato ,  Yukuya Tokumaru ,  Masanori Nakai

IPC分类号： H03K3/282 ,  G01D5/248 ,  G01K7/24 ,  G01R17/00 ,  H03K3/02 ,  H03K3/03 ,  H03K5/15 ,  H03M1/00

CPC分类号： G01D5/248 ,  G01K7/245 ,  G01R17/00 ,  H03K3/03 ,  H03M1/86

摘要： A measuring apparatus comprises: a first series circuit having first and second resistors connected between a power source terminal and ground; a second series circuit having a thermistor and a third resistor connected between the power source and ground; a first variable frequency oscillator for generating a pulse signal with the frequency corresponding to the current derived from the junction between the first and second resistors of the first series circuit; a second variable frequency oscillator for generating a pulse signal with the frequency corresponding to the current derived from the junction between the thermistor and the third resistor; a first counter which counts the pulse signal from the second variable frequency oscillator to produce a high level signal till it counts a given number of pulses; and AND gate connected to the output terminal of the first variable frequency oscillator and the first counter, a second counter for counting the pulse fed from the first variable frequency oscillator via the AND gate; and a display circuit for displaying the contents of the counter. The first and second variable oscillating circuits each have an odd number of inverters which are cascade-connected and each formed of an integrated injection logic circuit with a power receiving terminal connected to the first or second series circuit, the output terminal of the last stage inverter being connected to the input terminal of the first stage inverter.

摘要翻译： 一种测量装置包括：第一串联电路，其具有连接在电源端子和地之间的第一和第二电阻器; 第二串联电路，具有连接在电源和地之间的热敏电阻和第三电阻; 第一可变频率振荡器，用于产生具有与从第一串联电路的第一和第二电阻器之间的结点导出的电流的频率的脉冲信号; 第二可变频率振荡器，用于产生具有与从热敏电阻和第三电阻器之间的结点导出的电流相对应的频率的脉冲信号; 计数来自第二可变频率振荡器的脉冲信号以产生高电平信号的第一计数器，直到它计数给定数量的脉冲; 和与门连接到第一可变频率振荡器的输出端和第一计数器，第二计数器，用于通过与门对从第一可变频率振荡器馈送的脉冲进行计数; 以及显示计数器的内容的显示电路。 第一和第二可变振荡电路各自具有串联连接的奇数个反相器，并且每个都由具有连接到第一或第二串联电路的电力接收端子的集成注入逻辑电路，最后一级反相器的输出端子 连接到第一级逆变器的输入端子。

公开(公告)号：US4110634A

公开(公告)日：1978-08-29

申请号：US712668

申请日：1976-08-09

申请人： Yukuya Tokumaru ,  Masanori Nakai

发明人： Yukuya Tokumaru ,  Masanori Nakai

IPC分类号： H01L27/02 ,  H03K19/084 ,  H03K19/091 ,  H03K19/08 ,  H03K19/20

CPC分类号： H01L27/0237 ,  H03K19/084 ,  H03K19/091

摘要： A gate circuit is constituted by a plurality of logical elements formed on the same P type semiconductor substrate. Each logical element is composed of an N type first region and P type second region formed by double diffusion in one of a plurality of P type isolated islands formed on a P type semiconductor substrate, and an N type isolating region and N type buried region surrounding the islands. The P type second region, N type first region and P type island constitute a first vertical PNP transistor by operating as an emitter, base and collector, respectively, while the N type first region, P type island and N type buried region constitute a second vertical NPN transistor by operating as an emitter, base and collector, respectively. In the plurality of logical elements, a Schottky diode is provided for each input section thereof. Connected to a connection point between an anode of this Schottky diode and a base of the second vertical NPN transistor of one logical element is a collector of that of another logical element. A collector of the second NPN transistor of one logical element constitutes an output section.

摘要翻译： 门电路由形成在同一P型半导体衬底上的多个逻辑元件构成。 每个逻辑元件由形成在P型半导体衬底上的多个P型隔离岛中的一个中的双扩散形成的N型第一区和P型第二区组成，N型隔离区和N型掩埋区围绕 岛屿。 P型第二区域，N型第一区域和P型岛分别通过作为发射极，基极和集电极而构成第一垂直PNP晶体管，而N型第一区域，P型岛状物和N型掩埋区域构成第二垂直PNP晶体管 垂直NPN晶体管分别作为发射极，基极和集电极工作。 在多个逻辑元件中，为其每个输入部分提供肖特基二极管。 连接到该肖特基二极管的阳极和一个逻辑元件的第二垂直NPN晶体管的基极之间的连接点是另一个逻辑元件的集电极。 一个逻辑元件的第二NPN晶体管的集电极构成输出部分。

公开(公告)号：US4091296A

公开(公告)日：1978-05-23

申请号：US746169

申请日：1976-11-30

申请人： Yasoji Suzuki ,  Yukuya Tokumaru ,  Masanori Nakai

发明人： Yasoji Suzuki ,  Yukuya Tokumaru ,  Masanori Nakai

IPC分类号： H03K3/286 ,  H01L21/822 ,  H01L21/8226 ,  H01L27/04 ,  H01L27/082 ,  H03K3/037 ,  H03K3/288 ,  H03K19/091

CPC分类号： H03K3/288

摘要： A semiconductor R-S flip-flop circuit comprises first and second input terminals, first and second output terminals, a first integrated injection logic unit consisting of a first transistor acting as a switching element and a second transistor acting as an injector, and a second integrated injection logic unit consisting of a third transistor acting as a switching element and a fourth transistor acting as an injector. The R-S flip-flop circuit further includes a first diode having a cathode connected to the first input terminal and an anode connected to the base of the first transistor, a second diode having a cathode connected to the second input terminal and an anode connected to the base of the third transistor, a third diode having an anode connected to the base of the first transistor and a cathode connected to the collector of the third transistor, and a fourth diode having an anode connected to the base of the third transistor and a cathode connected to the collector of the first transistor.

摘要翻译： 半导体RS触发器电路包括第一和第二输入端，第一和第二输出端，由充当开关元件的第一晶体管和充当注入器的第二晶体管组成的第一集成注入逻辑单元和第二集成注入 逻辑单元由用作开关元件的第三晶体管和用作注入器的第四晶体管组成。 RS触发器电路还包括具有连接到第一输入端子的阴极和连接到第一晶体管的基极的阳极的第一二极管，具有连接到第二输入端子的阴极和连接到第二晶体管的阳极的第二二极管 第三晶体管的基极，具有连接到第一晶体管的基极的阳极和连接到第三晶体管的集电极的阴极的第三二极管，以及连接到第三晶体管的基极的阳极和阴极的第四二极管 连接到第一晶体管的集电极。