发明授权
- 专利标题: Combined integrated injection logic and transistor-transistor logic microprocessor integrated circuit design
- 专利标题(中): 集成注入逻辑和晶体管晶体管逻辑微处理器集成电路设计
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申请号: US167614申请日: 1980-07-11
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公开(公告)号: US4396980A公开(公告)日: 1983-08-02
- 发明人: Hemraj K. Hingarh
- 申请人: Hemraj K. Hingarh
- 申请人地址: CA Mountain View
- 专利权人: Fairchild Camera & Instrument Corp.
- 当前专利权人: Fairchild Camera & Instrument Corp.
- 当前专利权人地址: CA Mountain View
- 主分类号: G06F9/32
- IPC分类号: G06F9/32 ; G06F9/30 ; G06F15/78 ; H01L27/02 ; H03K3/288 ; H03K3/289 ; H03K19/018 ; G06F3/00 ; G06F7/48
摘要:
A microprocessor integrated circuit design has improved partitioning between integrated injection logic (I.sup.2 L) and transistor-transistor logic (T.sup.2 L) in the integrated circuit. An information bus structure incorporating a bidirectional input and output buffer and a bidirectional input and output multiplexer minimizes the number of internal bus lines in the integrated circuit. An improved T.sup.2 - I.sup.2 L interface circuit and structure supplies a T.sup.2 L input to a plurality of I.sup.2 L input stages, each having a restricted cross-sectional area resistor element in the base of an I.sup.2 L input transistor. A storage register in the integrated circuit has a multiplexer portion provided at each flip-flop circuit of the register. A high speed feed forward flip-flop circuit is employed in registers of the integrated circuit where speed is critical. An improved voltage regulator and current source combination in a programmable logic array (PLA) reduces PLA temperature sensitivity. A pair of I.sup.2 L clocking pulse input transistors in a T.sup.2 L master-slave circuit avoids capacitive coupling problems and allows the master-slave circuit to operate over a much wider temperature range. A cycle counter for the micro-processor integrated circuit implemented as an improved ripple down counter requires a minimum number of gates while avoiding significant delay in operation.