公开(公告)号：US5166094A

公开(公告)日：1992-11-24

申请号：US539710

申请日：1990-06-18

申请人： Ashok K. Kapoor

发明人： Ashok K. Kapoor

IPC分类号： H01L21/8222 ,  H01L27/07 ,  H01L29/47 ,  H03K19/084

CPC分类号： H01L27/0766 ,  H01L21/8222 ,  H01L29/47 ,  H03K19/084 ,  Y10S148/011 ,  Y10S148/087

摘要： A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in required area, while achieving very high speeds. As a result of the savings in area, the buried layer capacitance of the gate is also reduced, which facilitates the high-speed operation of the circuit.

摘要翻译： 基极耦合逻辑门的特征在于直接形成在用于栅极的开关晶体管的基极区上的输入肖特基二极管。 这种逻辑提供灵活的电路布置并节省所需的面积，同时实现非常高的速度。 由于节省了面积，栅极的埋层电容也减小，这有利于电路的高速运行。

公开(公告)号：US4640004A

公开(公告)日：1987-02-03

申请号：US600163

申请日：1984-04-13

申请人： Michael E. Thomas ,  Madhukar B. Vora ,  Ashok K. Kapoor

发明人： Michael E. Thomas ,  Madhukar B. Vora ,  Ashok K. Kapoor

IPC分类号： H01L21/22 ,  H01L21/28 ,  H01L21/285 ,  H01L23/532 ,  H01L29/43 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/28061 ,  H01L23/53257 ,  H01L29/456 ,  H01L29/4941 ,  H01L2924/0002 ,  Y10S148/034 ,  Y10S438/909

摘要： A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.

公开(公告)号：US4594493A

公开(公告)日：1986-06-10

申请号：US517190

申请日：1983-07-25

申请人： Shane Harrah ,  William Phy

发明人： Shane Harrah ,  William Phy

IPC分类号： H01L21/60 ,  B23K20/00 ,  H01L21/607 ,  B23K31/00

CPC分类号： H01L24/85 ,  B23K20/007 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48451 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/78268 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L24/45 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15724 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/30105 ,  H01L2924/3025

摘要： The present invention relates to a method and apparatus for forming a ball bond between a fine wire such as aluminum wire and a surface with the ball bond being approximately radially symmetric about a principal axis of a portion of the wire. The apparatus may include a plurality of electrodes radially spaced about the wire to define gaps between each electrode and the tip of the wire and a plurality of resistance elements. A voltage source may be connected to form a circuit consisting of plural electrically parallel legs, each of which includes the series combination of a resistance element, an electrode and an arc path between the electrode and the tip of the wire. A molten ball is formed at the end of the wire when arcs are essentially simultaneously produced between the electrodes and the tip of the wire. In a preferred embodiment, the resistances of the resistance elements are approximately equal. In addition, the plurality of electrodes are preferably symmetrically spaced about the wire to define gaps of nearly equal length between each electrode and the tip of the wire.

摘要翻译： 本发明涉及一种用于在诸如铝线的细线之间形成球接合的方法和装置，并且所述球接头的表面围绕导线的一部分的主轴大致径向对称。 该设备可以包括围绕电线径向间隔开的多个电极，以限定每个电极和电线的尖端之间的间隙以及多个电阻元件。 电压源可以被连接以形成由多个电平行腿组成的电路，每个电极包括电极元件，电极和电极与线尖之间的电弧路径的串联组合。 当在电极和电极的尖端之间基本上同时产生电弧时，在电线的末端形成熔融的球。 在优选实施例中，电阻元件的电阻大致相等。 此外，多个电极优选地围绕电线对称地间隔开，以限定每个电极和电线末端之间几乎相等长度的间隙。

公开(公告)号：US4549064A

公开(公告)日：1985-10-22

申请号：US482122

申请日：1983-04-05

申请人： Michelangelo Delfino

发明人： Michelangelo Delfino

IPC分类号： H01L21/268 ,  H01L21/3105 ,  B23K26/00

CPC分类号： H01L21/3105 ,  H01L21/268

摘要： An argon-fluorine (ArF) excimer laser is used to selectively heat various Si.sub.3 N.sub.4 materials used in the manufacture of semiconductor devices to elevated temperatures while maintaining active device regions and electrical interconnects at relatively low temperatures, to, for example, anneal the structural layer, induce compositional changes or densification and/or flow of the silicon nitride-based material to round off sharp edges and stops, all without damaging or appreciably affecting the active regions and electrical interconnects of a semiconductor device.

摘要翻译： 氩 - 氟（ArF）准分子激光器用于将制造半导体器件中使用的各种Si 3 N 4材料选择性地加热到升高的温度，同时保持有源器件区域和电互连在相对低的温度下，例如退火结构层， 引起氮化硅基材料的组成变化或致密化和/或流动以使尖锐的边缘和停止，从而不破坏或明显地影响半导体器件的有源区和电互连。

公开(公告)号：US4493079A

公开(公告)日：1985-01-08

申请号：US409068

申请日：1982-08-18

申请人： John H. Hughes, Jr.

发明人： John H. Hughes, Jr.

IPC分类号： G01R31/317 ,  G01R31/319 ,  G06F11/00

CPC分类号： G01R31/31713 ,  G01R31/31908 ,  G01R31/31926

摘要： A method and system for loading test data into individual pin memories of an automatic digital test system, particularly of the in-circuit type. Test data in the form of test vectors are accessed from a test vector store simultaneously with the access of a digital test pin selection signal. The test pin selection signal accessed with the test data is then used to selectively load the test data into a pin memory identified by the pin selection signal, thereby permitting the loading of test data into any one of a group of individual pin memories. In the preferrred embodiment the test data, a test vector, is stored in a test vector store in association with a test pin selection signal. When the test vector is read from memory, the test pin selection signal is also read by the same address signal.

摘要翻译： 一种用于将测试数据加载到自动数字测试系统，特别是在线电路类型的各个引脚存储器中的方法和系统。 测试向量的形式的测试数据可以与测试向量存储器同时访问数字测试引脚选择信号。 然后用测试数据访问的测试引脚选择信号用于选择性地将测试数据加载到由引脚选择信号识别的引脚存储器中，从而允许将测试数据加载到一组单独的引脚存储器中的任何一个中。 在优选的实施例中，将测试数据（测试矢量）与测试引脚选择信号相关联地存储在测试向量存储器中。 当从存储器读取测试向量时，测试引脚选择信号也被相同的地址信号读取。

公开(公告)号：US4493060A

公开(公告)日：1985-01-08

申请号：US543228

申请日：1983-10-20

申请人： Ramesh C. Varshney

发明人： Ramesh C. Varshney

IPC分类号： G11C19/28 ,  H01L27/105 ,  G11C11/34

CPC分类号： H01L27/1057 ,  G11C19/287

摘要： An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.

摘要翻译： SPS CCD存储器使用串行寄存器中的两相时钟和并行寄存器中的纹波时钟，并行寄存器中的电荷交错输出到输出串行寄存器。 第一交替并行寄存器通过第一传输门和第一存储门耦合到输出寄存器，第二交替并行寄存器通过第二传输门和第二存储门耦合到输出寄存器。 第三存储栅极设置有每个第三存储栅极交替地从第一存储栅极和第二存储栅极接收电荷，第三栅极将电荷输送到输出寄存器的相同存储元件。 通过线性交错第一个交替并行寄存器和第二个并行寄存器的最末端，电荷交错在并行寄存器的最末端出现。

公开(公告)号：US4488166A

公开(公告)日：1984-12-11

申请号：US484070

申请日：1983-04-11

申请人： William I. Lehrer

发明人： William I. Lehrer

IPC分类号： H01L21/768 ,  H01L23/54 ,  H01L21/283 ,  H01L21/44

CPC分类号： H01L21/76889

摘要： A process and resulting structure are disclosed for forming vias in integrated circuit structures using metal silicide interconnections. A lower conductor is formed by sequentially depositing silicon and a refractory metal which reacts with the silicon to create a layer of metal silicide. A subsequent layer of silicon is deposited on the surface of the metal silicide. This layer of silicon is insulated from overlying layers by forming insulating material over desired regions of the layer of silicon. A second layer of metal is then deposited across the structure. In openings in the insulating material the metal reacts with the second layer of silicon to form a via of metal silicide. A final layer of silicon may be deposited to convert any remaining metal in the second layer of metal to metal silicide, and the structure annealed to lower its resistivity.

摘要翻译： 公开了一种用于在使用金属硅化物互连的集成电路结构中形成通孔的工艺和结果。 通过依次沉积硅和与硅反应产生一层金属硅化物的难熔金属形成下导体。 随后的硅层沉积在金属硅化物的表面上。 该硅层通过在硅层的所需区域上形成绝缘材料而与上覆层绝缘。 然后在结构上沉积第二层金属。 在绝缘材料的开口中，金属与第二层硅反应形成金属硅化物的通孔。 可以沉积最终的硅层以将第二层金属中的任何剩余金属转化为金属硅化物，并且退火该结构以降低其电阻率。

公开(公告)号：US4481430A

公开(公告)日：1984-11-06

申请号：US404318

申请日：1982-08-02

申请人： William R. Houk ,  Hayagriva V. Rao

发明人： William R. Houk ,  Hayagriva V. Rao

IPC分类号： G06F1/28 ,  G06F1/26 ,  H03K17/22 ,  H03K19/082 ,  H03K17/30 ,  H03K17/62 ,  H03K19/007

CPC分类号： H03K19/0826 ,  H03K17/22 ,  H03K2017/226

摘要： An improved tristate enable circuit is described for activating a tristate enable gate to maintain the high impedance third state of a common bus tristate output device during "power down" and "power up" transitions of the common power supply V.sub.cc. The enable gate circuit element tends to turn off at a voltage level V.sub.cc2 generally greater than the voltage level V.sub.cc3 at which the tristate output device circuit elements turn off. As a result the high impedance state may be lost during "power down". A threshold activation circuit is coupled to the enable gate for activating the enable gate when the threshold activation circuit senses a higher common power supply voltage level V.sub.cc1. The threshold activation circuit operatively activates the enable gate over a voltage range from V.sub.cc1 to a lesser common power supply voltage level V.sub.cc4. Component values are selected for relating the voltage levels so that V.sub.cc1 >V.sub.cc2 and V.sub.cc3 >V.sub.cc4. As a result the turn off of circuit elements is sequenced by the threshold activation circuit.

摘要翻译： 描述了一种改进的三态使能电路，用于在公共电源Vcc的“断电”和“上电”转换期间激活三态使能门以保持公共总线三态输出设备的高阻抗第三状态。 使能栅极电路元件趋向于在三态输出器件电路元件关断的电压电平Vcc3的电压电平Vcc2处一般大于电压电平Vcc3。 因此，在“断电”期间，高阻抗状态可能会丢失。 当阈值激活电路感测到更高的公共电源电压电平Vcc1时，门限激活电路耦合到使能门，用于激活使能栅极。 门限激活电路在Vcc1到较小的公共电源电压电平Vcc4的电压范围内可操作地激活使能栅极。 选择元件值以使电压电平相关，使Vcc1> Vcc2和Vcc3> Vcc4。 结果，门限激活电路对电路元件的关断进行排序。

公开(公告)号：US4476546A

公开(公告)日：1984-10-09

申请号：US360029

申请日：1982-03-19

申请人： Ramesh C. Varshney

发明人： Ramesh C. Varshney

IPC分类号： G11C11/413 ,  G11C8/06 ,  G11C8/12 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00 ,  G11C11/34

CPC分类号： G11C29/78 ,  G11C8/06 ,  G11C8/12

摘要： A programmable address buffer for coupling external addresses to a desired pair of internal memory addresses includes A and B address inputs 11 and 12, a B address output 15 coupled to the B address input 12, a first inverter I30 coupled to the B address input and a B address output, a first switch S2 coupled to switchably connect one of the A and B address inputs 11 and 12 to a node, an A address output coupled to the first node, a second inverter I10 connected to the first node, a third inverter I20 connected between the second node and an A output 14, and a second switch S1 coupled to the second node to switchably connect one of the first node or the second inverter I10 to the second node.In another embodiment an electrical circuit for controlling the addressing of functional sections of a partially functional product includes a first pin 100 coupled by a first fuse F.sub.1 to a first address buffer 150, and a second pin 110 coupled by a second fuse F.sub.5 to a second address buffer 160, a fusible connection F.sub.4 between the second pin 110 and the first buffer 150, and fusible connections F.sub.2, F.sub.3, F.sub.6, and F.sub.7 to each address buffer to connect that address buffer to either of two selected potentials corresponding to the desired state of that buffer.

摘要翻译： 用于将外部地址耦合到期望的一对内部存储器地址的可编程地址缓冲器包括A和B地址输入11和12，耦合到B地址输入12的B地址输出15，耦合到B地址输入的第一反相器I30和 a和上行和B地址输出，第一开关S2，其耦合以将A和B地址输入端11和12中的一个可切换地连接到节点;耦合到第一节点的A地址输出;连接到第一节点的第二反相器I10; 连接在第二节点和上部＆amp; A输出端14之间的第三反相器I20和耦合到第二节点的第二开关S1，以将第一节点或第二逆变器I10之一可切换地连接到第二节点。 在另一个实施例中，用于控制部分功能产品的功能部分的寻址的电路包括通过第一熔丝F1耦合到第一地址缓冲器150的第一引脚100和通过第二熔丝F5耦合到第二引脚110的第二引脚110 地址缓冲器160，第二引脚110和第一缓冲器150之间的可熔连接F4以及到每个地址缓冲器的可熔连接F2，F3，F6和F7，以将该地址缓冲器连接到对应于期望状态的两个选择的电位 的那个缓冲区。

公开(公告)号：US4463270A

公开(公告)日：1984-07-31

申请号：US171762

申请日：1980-07-24

申请人： James S. Gordon

发明人： James S. Gordon

IPC分类号： G01R19/165 ,  G01R19/00 ,  G06F1/26 ,  G06F12/16 ,  H02J9/06 ,  H03K5/08 ,  H03K5/24 ,  H03K17/687 ,  H02J7/00 ,  H02J9/00 ,  H02J13/00

CPC分类号： H03K5/2472 ,  G01R19/0038

摘要： A circuit for detecting a difference in the relative magnitudes of two voltages includes a current sensing circuit connected between the first voltage and ground to thereby cause a first current to flow in the current sensing circuit, an amplifier connected between the second voltage and ground and connected to the current sensing circuit to thereby cause a second current to flow, the second current being equal to the first current when the first voltage is equal to the second voltage, and a variable impedance inverter connected to the first voltage and connected to the amplifier, the variable impedance being controlled by the first voltage, the output of the inverter thereby being related to the difference between the first voltage and the second voltage. The invention is particularly useful for controlling a battery backup power supply in a microprocessor having a volatile memory and for creating precision delay circuits.

摘要翻译： 用于检测两个电压的相对幅度差的电路包括连接在第一电压和地之间的电流感测电路，从而使第一电流在电流检测电路中流动，放大器连接在第二电压和地之间并连接 到电流感测电路，从而使第二电流流动，当第一电压等于第二电压时，第二电流等于第一电流，以及连接到第一电压并连接到放大器的可变阻抗逆变器， 所述可变阻抗由所述第一电压控制，所述逆变器的输出与所述第一电压和所述第二电压之间的差异相关。 本发明对于控制具有易失性存储器的微处理器中的电池备用电源以及用于创建精密延迟电路特别有用。