A parallel analog-to-digital converter circuit comprises a plurality of level comparator circuits and a plurality of detectors. The level comparator circuits compare the level of one analog input signal with a plurality of reference levels. Any two or more level comparator circuits which receive consecutive reference levels from one set. Each of the detectors determines whether or not the output signals from the level comparator circuits of one set are in a specified state. According to the number of sets of level comparator circuits whose output signals are detected to be in the specified state, it is determined whether or not the analog-to-digital converter circuit functions correctly. the upper limit of the speed of analog-to-digital conversion can be determined according to this number of sets.