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    MOS Parallel A/D converter
    1.
    发明授权
    MOS Parallel A/D converter 失效
    MOS并行A / D转换器

    公开(公告)号：US4547763A

    公开(公告)日：1985-10-15

    申请号：US503229

    申请日：1983-06-10

    申请人： Peter M. Flamm

    发明人： Peter M. Flamm

    IPC分类号： H03M1/36 ,  H03M1/00 ,  H04N7/24 ,  H03K13/175

    CPC分类号： H04N7/24 ,  H03M1/361

    摘要： For the dynamic compensation of the offset voltage in such converters each non-inverting comparator input (+) is connected via a first transfer transistor (T11, T12, T1p) to the signal input (SE) and via a second transfer transistor (T21, T22, T2p) to the associated voltage divider tap of the voltage divider as applied to the reference voltage (Ur). Moreover, each inverting comparator input (-), via a capacitor (C1, C2, Cp) is applied to the associated voltage divider tap and, via a third transfer transistor (T31, T32, T3p) and across a resistor (R'1, R'2, R'p) arranged in series therewith, to the associated comparator output. The second and third transfer transistors are rendered conductive during short intervals (T) between conversions by the clock signal (F), and the first transfer transistors are rendered non-conductive via the inverter (IV), and during the conversion time (t) the first transfer transistors are rendered conductive, and the second and third transfer transistors are rendered non-conductive. In television receivers, such MOS parallel A/D converters are suitable for processing the video signal, in which case the line sweep period serves as the conversion time (t), and the line fly-back period serves as the interval (T) between conversions.

    摘要翻译： 对于这种转换器中的偏移电压的动态补偿，每个非反相比较器输入（+）经由第一传输晶体管（T11，T12，T1p）连接到信号输入端（SE），并通过第二传输晶体管（T21， T22，T2p）连接到施加到参考电压（Ur）的分压器的相关分压器抽头。 此外，经由电容器（C1，C2，Cp）的每个反相比较器输入（ - ）被施加到相关联的分压器抽头，并且经由第三传输晶体管（T31，T32，T3p）和电阻器（R'1） ，R'2，R'p）连接到相关联的比较器输出。 第二传输晶体管和第三传输晶体管通过时钟信号（F）在转换之间的短间隔（T）期间导通，并且第一传输晶体管经由反相器（IV）变为非导通，并且在转换时间（t）期间， 第一传输晶体管导通，并且第二和第三传输晶体管变得不导通。 在电视接收机中，这种MOS并行A / D转换器适用于处理视频信号，在这种情况下，线路扫描周期用作转换时间（t），并且线路回放周期作为间隔（T） 转换。

    Voltage comparator using unequal gate width FET's
    2.
    发明授权
    Voltage comparator using unequal gate width FET's 失效
    电压比较器使用不等的栅极FET

    公开(公告)号：US4420743A

    公开(公告)日：1983-12-13

    申请号：US334257

    申请日：1981-12-24

    申请人： Lakshminarasimha C. Upadhyayula

    发明人： Lakshminarasimha C. Upadhyayula

    IPC分类号： H03K17/687 ,  H03K17/693 ,  H03M1/00 ,  H03K13/02 ,  H03K13/175

    CPC分类号： H03K17/693 ,  H03K17/687 ,  H03M1/361

    摘要： The threshold comparator includes a switching FET including a gate electrode and a load FET connected in series across a source of potential where the load FET is configured to provide a saturation current less than that of the switching FET with a first input level to the gate electrode and provide a saturation current greater than that of the switching FET with a second input level to the gate electrode. The output voltage of the switching FET changes value abruptly when the input level at its gate electrode attains the second input level where the saturation current in the switching FET is less than the saturation current of the load FET.

    摘要翻译： 阈值比较器包括开关FET，其包括栅极电极和负载FET串联连接在电源上，其中负载FET被配置为提供小于开关FET的饱和电流，其具有到栅电极的第一输入电平 并且向栅电极提供具有比开关FET的饱和电流大的第二输入电平的饱和电流。 当栅极电极的输入电平达到开关FET中的饱和电流小于负载FET的饱和电流的第二输入电平时，开关FET的输出电压突然变化。

    Digital display circuit displayable in analog fashion
    3.
    发明授权
    Digital display circuit displayable in analog fashion 失效
    数字显示电路以模拟方式显示

    公开(公告)号：US4365236A

    公开(公告)日：1982-12-21

    申请号：US176579

    申请日：1980-08-08

    申请人： Osamu Maida

    发明人： Osamu Maida

    IPC分类号： G01R13/02 ,  G01R19/257 ,  H03M1/00 ,  H03K13/175

    CPC分类号： G01R19/257 ,  G01R13/02 ,  H03M1/361

    摘要： A display circuit for displaying analog input voltages in a digital fashion using a parallel comparison type analog-digital converter includes a voltage generator for generating a plurality of reference voltages quantized at a predetermined voltage width, a plurality of comparators corresponding to the plurality of reference voltages for comparing the reference voltages and an analog input voltage as input, and display means for encoding and displaying the output of the plurality of comparators, is provided with modulating apparatus for modulating one of the inputs of each of the plurality of comparators periodically within the range of the predetermined voltage width.

    摘要翻译： 一种使用并行比较型模拟数字转换器以数字方式显示模拟输入电压的显示电路包括用于产生以预定电压宽度量化的多个参考电压的电压发生器，对应于多个参考电压的多个比较器 用于比较参考电压和作为输入的模拟输入电压，以及用于对多个比较器的输出进行编码和显示的显示装置，具有用于在该范围内周期性地调制多个比较器中的每一个的输入中的一个的调制装置 的预定电压宽度。

    Indicator arrangement utilizing analog-digital converter
    4.
    发明授权
    Indicator arrangement utilizing analog-digital converter 失效
    使用模拟数字转换器的指示灯布置

    公开(公告)号：US4262282A

    公开(公告)日：1981-04-14

    申请号：US907613

    申请日：1978-05-19

    申请人： Osamu Maida

    发明人： Osamu Maida

    IPC分类号： G01R13/02 ,  G01R19/17 ,  H03M1/00 ,  H03K13/175

    CPC分类号： G01R19/17 ,  G01R13/02 ,  H03M1/802 ,  H03M1/361

    摘要： An indicator arrangement includes comparators for parallel comparison of an analog input voltage with digitalizing standard voltages to digitalize the input voltage and an indicator for indicating digitalized output. The arrangement is provided with a controller periodically switched between a first control state and a second control state. The controller in the first control state allows the comparators to perform comparison in a first voltage range of the analog input voltage while in the second control state it allows the comparators to perform comparison in a second voltage range of the analog input voltage.There is provided an encoder for coding the digitalized output of the comparators with a first coding mode in the first control state of the controller and coding the digitalized output of the comparators with a second coding mode in the second control state. The encoder is adapted to drive the indicator with a first or second mode according to the state of the controller.

    摘要翻译： 指示器装置包括用于将模拟输入电压与数字化标准电压并行比较以将数字化输入电压的比较器和用于指示数字化输出的指示器。 该装置设置有在第一控制状态和第二控制状态之间周期性切换的控制器。 处于第一控制状态的控制器允许比较器在模拟输入电压的第一电压范围内进行比较，而在第二控制状态下，允许比较器在模拟输入电压的第二电压范围内执行比较。 提供了一种用于在控制器的第一控制状态下以第一编码模式对比较器的数字化输出进行编码的编码器，并且在第二控制状态下以第二编码模式对比较器的数字化输出进行编码。 编码器适于根据控制器的状态以第一或第二模式驱动指示器。

    Parallel-serial analog to digital converters
    5.
    发明授权
    Parallel-serial analog to digital converters 失效
    并行串行模数转换器

    公开(公告)号：US4131885A

    公开(公告)日：1978-12-26

    申请号：US681507

    申请日：1976-04-29

    申请人： Takeshi Ninomiya

    发明人： Takeshi Ninomiya

    IPC分类号： H03M1/14 ,  H03M1/00 ,  H03K13/175

    CPC分类号： H03M1/462

    摘要： In an analog to digital converter in which each sampled portion of an incoming video or other analog signal is converted to a digital character in a plurality of parallel conversions occurring serially; the range of the voltage level reference signals of descending magnitude which are applied to comparators for effecting a relatively fine parallel conversion of a sampled analog signal is selected to be larger than, and offset in respect, to the steps or increments of the voltage level reference signals of descending magnitude which are applied to comparators for effecting a preceding relatively coarser parallel conversion, and the encoded outputs from the serially occurring parallel conversions are digitally added with the least significant bit of the encoded output from each preceding relatively coarser parallel conversion being accorded the same weight as the most significant bit of the encoded output from the next following relatively finer parallel conversion so as to eliminate from the result of the digital addition defects that would otherwise arise from inaccuracies in the voltage level reference signals and/or in the comparing operations of the comparators.

    摘要翻译： 在模数转换器中，其中输入视频或其他模拟信号的每个采样部分以串行发生的多个并行转换转换为数字字符; 选择施加到比较器的用于进行采样的模拟信号的相对精细的并行转换的下降幅度的电压电平参考信号的范围大于和相对于电压电平基准的步长或增量的偏移 施加到比较器的下降幅度的信号用于实现先前相对较粗略的并行转换，并且来自串行发生的并行转换的编码输出被数字地相加，其中来自每个先前相对较粗略的并行转换的编码输出的最低有效位符合 与来自下一次相对更精细的并行转换的编码输出的最高有效位相同的权重，以便消除否则将由于电压电平参考信号的不准确性和/或比较操作而产生的数字加法缺陷的结果 的比较。

    Analog to digital converter
    6.
    发明授权
    Analog to digital converter 失效
    模数转换器

    公开(公告)号：US3968486A

    公开(公告)日：1976-07-06

    申请号：US481158

    申请日：1974-06-20

    申请人： Richard C. Gerdes

    发明人： Richard C. Gerdes

    IPC分类号： H03M1/00 ,  H03K13/175

    CPC分类号： H03M1/361

    摘要： An electronic analog to digital converter utilizing a plurality of analog comparators, all comparators receiving a common analog input and separate respective reference voltages for comparison. The outputs of the comparators provide respectively the digital word output of the analog to digital converter wherein the output state of the comparators are dependent upon the output state of the prior higher order comparator and where the resolution of the analog to digital converter is dependent on the number of stages of comparators utilized. The referenced voltage for the least significant digital bit is determined by all prior, high order digital output. The analog to digital converter disclosed is of the asynchronous type not requiring a clock signal and the total analog to digital conversion time is nT.sub.c, where n is the number of comparator stages and T.sub.c is the response time of the comparator.

    摘要翻译： 一种利用多个模拟比较器的电子模数转换器，所有比较器接收公共模拟输入，并分离各个参考电压进行比较。 比较器的输出分别提供模数转换器的数字字输出，其中比较器的输出状态取决于先前较高阶比较器的输出状态，并且模数转换器的分辨率取决于 使用比较器的阶段数。 最低有效数字位的参考电压由所有先前的高阶数字输出决定。 所公开的模数转换器是不需要时钟信号的异步型转换器，总模数转换时间是nTc，其中n是比较器级数，Tc是比较器的响应时间。

    Multithreshold analog to digital converter
    8.
    发明授权
    Multithreshold analog to digital converter 失效
    MULTITHRESHOLD模拟到数字转换器

    公开(公告)号：US3806915A

    公开(公告)日：1974-04-23

    申请号：US28638172

    申请日：1972-09-05

    申请人： US NAVY

    发明人： HIGGINS R ,  SPETNER L

    IPC分类号： H03M1/00 ,  H03K13/175

    CPC分类号： H03M1/361

    摘要： A method and apparatus for performing high speed conversion of an analog signal into a binary digital code. The analog input signal is applied simultaneously to a plurality of threshold detectors each associated with a preselected different discrete analog signal level and whose output signals are combined according to a novel logic algorithm to produce the multi-bit digital binary output Gray code or straight binary code with a minimum of time consuming serially connected circuit operations or elements.

    摘要翻译： 一种用于将模拟信号高速转换成二进制数字码的方法和装置。 模拟输入信号同时施加到多个阈值检测器，每个阈值检测器与预选的不同分立模拟信号电平相关联，并且其输出信号根据新颖的逻辑算法组合以产生多位数字二进制输出格雷码或直二进制码 具有最少的耗时的串行连接的电路操作或元件。

    Apparatus for converting a cyclic analog signal to a digital signal
    9.
    发明授权
    Apparatus for converting a cyclic analog signal to a digital signal 失效
    将循环模拟信号转换为数字信号的装置

    公开(公告)号：US3656154A

    公开(公告)日：1972-04-11

    申请号：US3656154D

    申请日：1970-09-09

    申请人： POTTER INSTRUMENT CO INC

    发明人： ROSS JOSEPH A ,  HEMDAL HAKAN O

    IPC分类号： G06K11/00 ,  H03M1/00 ,  H03K13/175

    CPC分类号： G06K11/00 ,  H03M1/30

    摘要： The specification and drawings disclose 10 photocells arranged to view a full cycle of a space distributed analog signal. Each photocell is coupled to the input of an amplifier whose output rests in one binary state if the input exceeds one level and rests in another binary state if its input falls below another level. Of the large number of combinations in which the binary outputs of the amplifiers can exist, logic circuitry responsive to certain combinations only produces one unique output for each incremental displacement of the periodically varying signal.

    摘要翻译： 本说明书和附图公开了10个光电管，用于查看空间分布式模拟信号的整个周期。 每个光电池耦合到放大器的输入端，如果输入超过一个电平，则其输出处于一个二进制状态，如果其输入降低到另一个电平，则放置在另一个二进制状态。 在可以存在放大器的二进制输出的大量组合中，响应于某些组合的逻辑电路仅为周期性变化信号的每个增量位移产生唯一的输出。