公开(公告)号：US4560890A

公开(公告)日：1985-12-24

申请号：US526821

申请日：1983-08-26

申请人： Eiji Masuda ,  Kenji Matsuo ,  Yasuhiko Fujita

发明人： Eiji Masuda ,  Kenji Matsuo ,  Yasuhiko Fujita

IPC分类号： H03M1/36 ,  G01R17/06 ,  H03K5/08 ,  H03K5/24

CPC分类号： G01R17/06 ,  H03K5/249

摘要： An input voltage sampler samples the difference between two input voltages. An alternate switch switches at a period which is longer than twice the sampling period. The voltage difference is supplied through the alternate switch to a plurality of amplifiers. Prior to starting the amplifying operation, operating point setting circuits set the input level to the amplifiers at the operating point.

摘要翻译： 输入电压采样器对两个输入电压之间的差异进行采样。 交替开关的开关时间长于采样周期的两倍。 电压差通过交替开关提供给多个放大器。 在开始放大操作之前，工作点设置电路在工作点将输入电平设置为放大器。

公开(公告)号：US4600916A

公开(公告)日：1986-07-15

申请号：US487131

申请日：1983-04-21

申请人： Eiji Masuda ,  Kenji Matsuo ,  Yasuhiko Fujita

发明人： Eiji Masuda ,  Kenji Matsuo ,  Yasuhiko Fujita

IPC分类号： H03M1/36 ,  H03K5/08 ,  H03M1/00 ,  H03M1/10 ,  H03K13/175

CPC分类号： H03K5/08 ,  H03M1/1071 ,  H03M1/361

摘要： A parallel analog-to-digital converter circuit comprises a plurality of level comparator circuits and a plurality of detectors. The level comparator circuits compare the level of one analog input signal with a plurality of reference levels. Any two or more level comparator circuits which receive consecutive reference levels from one set. Each of the detectors determines whether or not the output signals from the level comparator circuits of one set are in a specified state. According to the number of sets of level comparator circuits whose output signals are detected to be in the specified state, it is determined whether or not the analog-to-digital converter circuit functions correctly. the upper limit of the speed of analog-to-digital conversion can be determined according to this number of sets.

摘要翻译： 并行模数转换器电路包括多个电平比较器电路和多个检测器。 电平比较器电路将一个模拟输入信号的电平与多个参考电平进行比较。 任何两个或多个电平比较器电路，从一组接收连续的参考电平。 每个检测器确定来自一组的电平比较器电路的输出信号是否处于指定状态。 根据其输出信号被检测为处于指定状态的电平比较器电路的数量，确定模数转换器电路是否正常工作。 模数转换速度的上限可以根据这个数量来确定。

公开(公告)号：US4639554A

公开(公告)日：1987-01-27

申请号：US685834

申请日：1984-12-24

申请人： Eiji Masuda ,  Yasuhiko Fujita

发明人： Eiji Masuda ,  Yasuhiko Fujita

IPC分类号： H04M1/50 ,  H03K1/16 ,  G06F15/20

CPC分类号： H04M1/505

摘要： A dual-tone multiple-frequency (DTMF)-signal generating apparatus of the present invention is provided with a high-group frequency divider and a low-group frequency divider for dividing a reference frequency signal into high-group frequencies and low-group frequencies, respectively. The respective outputs from the high-group divider and the low-group divider are supplied to a high-group-sine-wave-signal generator and a low-group-sine-wave-signal generator. The high- and low-group-sine-wave-signal generators comprise a plurality of bi-stable circuits and include shift registers for sequentially shifting a divided input signal within a predetermined period, a plurality of switches which selectively pass high or low level signal corresponding to the outputs of the respective bi-stable circuits, and a plurality of capacitive elements in which the terminals on one side thereof are supplied with the high or low level passed by the plurality of switches, and the terminals on the other side thereof are commonly connected, the high or low level being applied to the comon connection for every cycle of the shift registers to produce the high- and low-group-sine-wave signals from the common connection. The respective sine wave signals are level converting by a high-group level converter comprising a capacitor and a switch and by a low-group level converter comprising a capacitor and a switch. The level converted high- and low-group-sine-wave signals are combined by a mixer comprising buffer amplifiers, resistors and a transistor, thereby obtaining a DTMF signal.

摘要翻译： 本发明的双音多频（DTMF）信号发生装置具有高分组分频器和低组分频器，用于将参考频率信号分成高组频率和低组频率 ， 分别。 来自高分组分频器和低组分频器的相应输出被提供给高组正弦波信号发生器和低组正弦波信号发生器。 高和低组正弦波信号发生器包括多个双稳态电路，并且包括用于在预定周期内顺序移位分频输入信号的移位寄存器，选择性地通过高电平或低电平信号的多个开关 对应于各个双稳态电路的输出，以及多个电容元件，其中一侧的端子被提供有多个开关通过的高电平或低电平，而另一侧的端子是 通常连接，高电平或低电平被施加到移位寄存器的每个周期的comon连接，以从公共连接产生高和低组正弦波信号。 相应的正弦波信号是由包括电容器和开关的高组电平转换器和包括电容器和开关的低组电平转换器进行电平转换。 电平转换的高和低组正弦波信号由包括缓冲放大器，电阻器和晶体管的混频器组合，从而获得DTMF信号。

公开(公告)号：US4665381A

公开(公告)日：1987-05-12

申请号：US601247

申请日：1984-04-17

申请人： Eiji Masuda ,  Yasuhiko Fujita

发明人： Eiji Masuda ,  Yasuhiko Fujita

IPC分类号： H03M1/76 ,  H03M1/00 ,  H03K13/02

CPC分类号： H03M1/808 ,  H03M1/365

摘要： In a D/A converter, a reference voltage is divided into a plurality of divided voltages by a plurality of resistors connected in series. The divided voltages are respectively selected by switches which are turned on according to the contents of a digital input. With the use of an expanding bit or bits, a plurality of the switches are simultaneously turned on.

摘要翻译： 在D / A转换器中，通过串联连接的多个电阻将参考电压分成多个分压。 根据数字输入的内容，开关分别选择分压。 通过使用扩展位或位，多个开关同时导通。

公开(公告)号：US4841567A

公开(公告)日：1989-06-20

申请号：US246965

申请日：1988-09-21

申请人： Eiji Masuda ,  Yasuhiko Fujita ,  Terufumi Takasaki

发明人： Eiji Masuda ,  Yasuhiko Fujita ,  Terufumi Takasaki

IPC分类号： H04M1/274 ,  G11C7/10 ,  H01L27/10 ,  H04M1/2745

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1051 ,  H04M1/2745

摘要： The memory device memorizes a number corresponding to a plurality of digits, for example, a unit phone number using a first memory array. A desired number is obtained by selecting a Y address. A readout operation is executed by inputting whole data selected by a Y address to a second memory array at once and outputting data sequentially from the second memory array by one digit. A write operation is executed by inputting data sequentially to the second memory array by one digit and outputting data from the second memory array to the first memory array at once.

摘要翻译： 存储装置使用第一存储器阵列存储对应于多个数字的号码，例如，单位电话号码。 通过选择Y地址获得所需数量。 通过将由Y地址选择的整个数据一次输入到第二存储器阵列并将数据从第二存储器阵列依次输出一位数来执行读出操作。 通过将数据顺序地输入到第二存储器阵列一位并且将数据从第二存储器阵列立即输出到第一存储器阵列来执行写入操作。

公开(公告)号：US4539551A

公开(公告)日：1985-09-03

申请号：US518443

申请日：1983-07-29

申请人： Yasuhiko Fujita ,  Eiji Masuda

发明人： Yasuhiko Fujita ,  Eiji Masuda

IPC分类号： H03K5/24 ,  H03M1/00 ,  H03K13/02 ,  H03K3/023

CPC分类号： H03K5/249 ,  H03M1/361

摘要： A differential voltage amplifier comprises a first and second capacitive coupling type amplifiers in each of which an autozeroed mode period for setting an operating point and a signal amplifying mode period for amplifying an input voltage are alternately set up, and the autozeroed mode periods in said first and second amplifier are shifted from each other, first and second mode selector for alternately setting up the autozeroed mode and the signal amplifying mode in the first and second capacitive coupling type amplifiers, first and second signal selectors provided corresponding to the first and second capacitive coupling type amplifiers, the first and second signal selectors alternately selecting a reference voltage and an input signal voltage to apply the selected signal to the first and second capacitive coupling type amplifiers, the first and second signal selectors further selecting the reference voltage corresponding to the autozeroed mode periods of the first and second capacitive coupling type amplifiers and the input signal voltage corresponding to the signal amplifying mode periods, and a selector for selecting the amplified signal output from the first and second capacitive coupling type amplifiers when the first and second capacitive coupling type amplifiers are in the signal amplifying mode.

摘要翻译： 差分电压放大器包括第一和第二电容耦合型放大器，其中每个放大器交替地设置用于设置工作点的自动调零模式周期和用于放大输入电压的信号放大模式周期，并且所述第一和第二电容耦合型放大器中的自动调零模式周期 并且第二放大器彼此偏移，第一和第二模式选择器，用于在第一和第二电容耦合型放大器中交替地设置自动归零模式和信号放大模式，第一和第二信号选择器对应于第一和第二电容耦合 第一和第二信号选择器交替地选择参考电压和输入信号电压以将所选择的信号施加到第一和第二电容耦合型放大器，第一和第二信号选择器进一步选择对应于自动归零模式的参考电压 第一和第二电容的周期 耦合型放大器和对应于信号放大模式周期的输入信号电压;以及选择器，用于当第一和第二电容耦合型放大器处于信号放大模式时，选择从第一和第二电容耦合型放大器输出的放大信号 。

公开(公告)号：US4511814A

公开(公告)日：1985-04-16

申请号：US445038

申请日：1982-11-29

申请人： Kenji Matsuo ,  Eiji Masuda

发明人： Kenji Matsuo ,  Eiji Masuda

IPC分类号： H03K17/14 ,  H03K17/687 ,  H03K17/16 ,  H03K17/693 ,  H03K19/096

CPC分类号： H03K17/6872 ,  H03K17/145

摘要： A semiconductor analog switch circuit device is disclosed in which a second analog switch circuit is connected in parallel with a first analog switch circuit. The first and second switch circuits are controlled by control pulses with opposite phases. An input signal is applied to one of the parallel junctions of the first and second analog switch circuits, while an output signal is derived from the other parallel junction.

摘要翻译： 公开了一种半导体模拟开关电路装置，其中第二模拟开关电路与第一模拟开关电路并联连接。 第一和第二开关电路由具有相反相位的控制脉冲控制。 输入信号施加到第一和第二模拟开关电路的并联结之一，而输出信号则从另一个并联结导出。

公开(公告)号：US4656429A

公开(公告)日：1987-04-07

申请号：US455797

申请日：1983-01-05

申请人： Eiji Masuda ,  Kenji Matsuo

发明人： Eiji Masuda ,  Kenji Matsuo

IPC分类号： H03F3/34 ,  H03F3/16 ,  H03K5/08 ,  H03K5/24 ,  H03K5/22 ,  H03B1/00

CPC分类号： H03K5/249

摘要： A voltage comparison circuit having an amplification circuit which includes an inverting amplifier and a switching MOS transistor for setting an operation point of the inverting amplifier connected between input and output terminals of the inverting amplifier. The amplification circuit further includes at least one low-pass filter connected in a closed loop including the inverting amplifier and the switching MOS transistor.

摘要翻译： 一种具有放大电路的电压比较电路，包括反相放大器和开关MOS晶体管，用于设置连接在反相放大器的输入和输出端之间的反相放大器的操作点。 放大电路还包括连接在包括反相放大器和开关MOS晶体管的闭环中的至少一个低通滤波器。

公开(公告)号：US4633101A

公开(公告)日：1986-12-30

申请号：US735291

申请日：1985-05-17

申请人： Eiji Masuda ,  Kenji Matsuo

发明人： Eiji Masuda ,  Kenji Matsuo

IPC分类号： H01L21/822 ,  H01L27/04 ,  H01L29/78 ,  H03K5/24 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/096

CPC分类号： H03K17/063 ,  H03K17/162 ,  H03K17/687 ,  H03K5/249

摘要： A semiconductor switching circuit includes a MOS inverter and a switching MOS transistor for executing a switching operation in response to the output signal from the MOS inverter. The semiconductor switching circuit further includes a low-pass filter coupled between the MOS inverter and the gate of the switching MOS transistor.

摘要翻译： 半导体开关电路包括MOS反相器和开关MOS晶体管，用于响应于来自MOS反相器的输出信号执行开关操作。 半导体开关电路还包括耦合在MOS反相器和开关MOS晶体管的栅极之间的低通滤波器。

公开(公告)号：US4524327A

公开(公告)日：1985-06-18

申请号：US394615

申请日：1982-07-02

申请人： Eiji Masuda ,  Kenji Matsuo

发明人： Eiji Masuda ,  Kenji Matsuo

IPC分类号： H03F1/34 ,  H03F1/08 ,  H03F3/34 ,  H03F3/45

CPC分类号： H03F1/086

摘要： An operational amplifier which comprises a first amplifying circuit; a second amplifying circuit which is connected to the first amplifying circuit and carries out inverting amplification; a third amplifying circuit which is connected to the second amplifying circuit, carries out noninverting amplification and has a gain of substantially 1; a first feedback circuit which is connected between the output and input terminals of the second amplifying circuit and carries out phase-compensation; and a second feedback circuit which is connected between the output terminal of the third amplifying circuit and the input terminal of the second amplifying circuit, and carries out phase-compensation.

摘要翻译： 一种运算放大器，包括第一放大电路; 第二放大电路，连接到第一放大电路并执行反相放大; 连接到第二放大电路的第三放大电路执行非反相放大并具有大致1的增益; 第一反馈电路，连接在第二放大电路的输出端和输入端之间，进行相位补偿; 以及第二反馈电路，其连接在第三放大电路的输出端子和第二放大电路的输入端子之间，并进行相位补偿。