发明授权
US4843596A Semiconductor memory device with address transition detection and timing
control
失效
具有地址转换检测和定时控制的半导体存储器件
- 专利标题： Semiconductor memory device with address transition detection and timing control
- 专利标题（中）： 具有地址转换检测和定时控制的半导体存储器件
-
申请号： US124554申请日： 1987-11-24
-
公开(公告)号： US4843596A公开(公告)日： 1989-06-27
- 发明人: Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
- 申请人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
- 申请人地址： JPX
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JPX
- 优先权： JPX61-284849 19861129
- 主分类号： G11C11/401
- IPC分类号： G11C11/401 ; G11C7/22 ; G11C8/18
摘要：
A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.
公开/授权文献
- US5333577A Variable valve operation timing control device 公开/授权日：1994-08-02
信息查询
