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    Dynamic random access memory with well-balanced read-out voltage on bit line pair and operating method therefor
    1.
    发明授权
    Dynamic random access memory with well-balanced read-out voltage on bit line pair and operating method therefor 失效
    动态随机存取存储器，位线对上的平衡读出电压及其操作方法

    公开(公告)号：US4982367A

    公开(公告)日：1991-01-01

    申请号：US192575

    申请日：1988-05-11

    申请人： Hideshi Miyatake

    发明人： Hideshi Miyatake

    IPC分类号： G11C11/409 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A DRAM comprises equalizing capacitance for equalizing the difference between a potential on a bit line to which a selected memory cell is connected and a potential on a reference bit line paired with the bit line when the selected memory cell stores "H" information and that when the selected memory cell stores "L" information, before sensing operation is started. The amplitude of a potential on a selected word line is at an operating power-supply voltage Vcc level of the DRAM.

    摘要翻译： DRAM包括均衡电容，用于在所选择的存储单元存储“H”信息时均衡与连接选定存储单元的位线上的电位和与位线配对的参考位线上的电位之间的差值，以及当 在开始感测操作之前，所选存储单元存储“L”信息。 所选字线上的电位的幅度处于DRAM的工作电源电压Vcc电平。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4760559A

    公开(公告)日：1988-07-26

    申请号：US883311

    申请日：1986-07-08

    申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka

    发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka

    IPC分类号： G11C11/407 ,  G11C11/408 ,  G11C7/00

    CPC分类号： G11C11/4085

    摘要： A dynamic type MOS-RAM constructed of folded type bit lines and having sense operation cycles for amplifying potential difference appearing on respective pairs of bit lines after selection of a word line and restore operation cycles for further amplifying the potential difference on the pairs of bit lines after the sense operation cycles, wherein non-selected word lines are completely brought into electrically floating states in intervals including the sense operation cycles and the restore operation cycles.

    摘要翻译： 由折叠型位线构成的具有读出操作周期的动态型MOS-RAM，用于放大在选择字线之后出现在各对位线上的电位差，并且还原操作周期用于进一步放大位线对上的电位差 在感测操作周期之后，其中未选择的字线在包括感测操作周期和恢复操作周期的间隔中完全进入电浮动状态。

    Semiconductor memory
    4.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US4692901A

    公开(公告)日：1987-09-08

    申请号：US762632

    申请日：1985-08-05

    申请人： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasumasa Nishimura

    发明人： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasumasa Nishimura

    IPC分类号： G11C29/34 ,  G11C7/00

    CPC分类号： G11C29/34

    摘要： A semiconductor memory comprises memory cells (15-18, 27-30), a data writing terminal (1), a data readout terminal (48), transistors (3-10, 35-42), address signal input terminals (23-26), subdecode signal input terminals (43-46), driving signal generating circuits (49-52), parallel readout circuits (79-82) and test mode switching signal input terminal (53, 88). In writing of function test data for the memory cells, the driving signal generating circuits turn all of the transistors (3-10) on in response to a test mode switching signal with no regard to address signals, thereby to simultaneously write data in the memory cells (15-18). Further, in readout of the function test data for the memory cells, the parallel readout circuits read the storage contents of the memory cells (27-30) storing the test data in response to a test mode switching signal with no regard to subdecode signals. Logic circuit means (90, 91, 94) may be provided to output logical value corresponding to the test data stored in the memory cells when all of the logical values of the test data are at the same level.

    摘要翻译： 半导体存储器包括存储单元（15-18,27-30），数据写入端（1），数据读出端（48），晶体管（3-10,35-42），地址信号输入端（23- 26），子代码信号输入端子（43-46），驱动信号发生电路（49-52），并行读出电路（79-82）和测试模式切换信号输入端子（53,88）。 在写入存储单元的功能测试数据时，驱动信号发生电路响应于测试模式切换信号而使所有晶体管（3-10）响应于地址信号，从而同时将数据写入存储器 细胞（15-18）。 此外，在读出存储单元的功能测试数据时，并行读出电路响应于不考虑子代码信号的测试模式切换信号读取存储测试数据的存储单元（27-30）的存储内容。 可以提供逻辑电路装置（90,91,94）以当测试数据的所有逻辑值处于相同电平时输出与存储在存储单元中的测试数据相对应的逻辑值。

    Semiconductor memory device with a laser programmable redundancy circuit
    5.
    发明授权
    Semiconductor memory device with a laser programmable redundancy circuit 失效
    具有激光可编程冗余电路的半导体存储器件

    公开(公告)号：US4658379A

    公开(公告)日：1987-04-14

    申请号：US666380

    申请日：1984-10-30

    申请人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake ,  Masahiro Tomisato

    发明人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake ,  Masahiro Tomisato

    IPC分类号： G11C8/10 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

    CPC分类号： G11C29/787 ,  G11C8/10

    摘要： A semiconductor memory device with a laser programmable redundancy circuit, which includes: a plurality of decoders for selecting a row or column of the memory; at least one spare decoder which is selected instead of a decoder connected to a faulty memory cell; a link element inserted in series with the precharging transistor and connected between the power supply and the decoder output line; a signal generator which generates a non-selection signal for making the object decoder unselected only when a spare decoder is selected, the signal generator being provided in the spare decoder; and a transistor, having a gate to which the non-selection signal is input, with the drain and the source thereof being connected to the decoder output and ground, respectively, the transistor being provided in the decoder.

    摘要翻译： 一种具有激光可编程冗余电路的半导体存储器件，包括：多个解码器，用于选择存储器的行或列; 选择代替连接到故障存储器单元的解码器的至少一个备用解码器; 与预充电晶体管串联插入并连接在电源和解码器输出线之间的连接元件; 信号发生器，其仅在选择了备用解码器时产生用于使对象解码器未选择的非选择信号，所述信号发生器设置在所述备用解码器中; 以及晶体管，其具有输入非选择信号的栅极，漏极和源极分别连接到解码器输出和接地，晶体管分别设置在解码器中。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4586167A

    公开(公告)日：1986-04-29

    申请号：US568138

    申请日：1984-01-04

    申请人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake

    发明人： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C13/00

    CPC分类号： G11C7/1045 ,  G11C7/22 ,  G11C8/18

    摘要： Disclosed is a semiconductor memory device which is operable in a selected one of page mode and nibble mode, depending upon the length of time in which an external column address strobe signal stays at a specific level. The semiconductor memory device comprises a circuit for discriminating the length of time where the external column address strobe signal is at a specific level with a predetermined period of time. Data is outputted in page mode in response to one of results of such discrimination and in nibble mode in response to the other result of the discrimination. The discriminating circuit may comprise a second internal column address strobe signal generator and a delay circuit. The second internal column address strobe signal generator includes a NAND circuit at its first stage, and the delay circuit is designed to have different delay times at the building-up and downward edges of an input signal applied thereto. The output of the discriminator is used to operate and reset an output circuit whereby one of the output modes is selected.

    摘要翻译： 公开了根据外部列地址选通信号保持在特定级别的时间长度，可以在页模式和半字节模式中选择的一个中操作的半导体存储器件。 半导体存储器件包括用于在预定时间段内鉴别外部列地址选通信号处于特定电平的时间长度的电路。 响应于这种歧视的结果之一，以页面模式输出数据，并且响应于歧视的另一结果，以半字节模式输出数据。 识别电路可以包括第二内部列地址选通信号发生器和延迟电路。 第二内部列地址选通信号发生器包括在其第一级的NAND电路，并且延迟电路被设计为在施加到其的输入信号的建立和向下边缘处具有不同的延迟时间。 鉴别器的输出用于操作和复位输出电路，由此选择一个输出模式。

    Semiconductor dynamic random access memory with relaxed pitch condition for sense amplifiers and method of operating the same
    7.
    发明授权
    Semiconductor dynamic random access memory with relaxed pitch condition for sense amplifiers and method of operating the same 失效
    用于读出放大器的松弛音调条件的半导体动态随机存取存储器及其操作方法

    公开(公告)号：US4980864A

    公开(公告)日：1990-12-25

    申请号：US282142

    申请日：1988-12-09

    申请人： Ryoji Fukuhama ,  Hideshi Miyatake

    发明人： Ryoji Fukuhama ,  Hideshi Miyatake

    IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097

    CPC分类号： G11C11/4097 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

    摘要： A semiconductor dynamic random access memory is provided comprising bit line pairs divided into groups and sense amplifiers, one for each bit line pair group provided on one side of the bit line pairs in a line. When a word line is selected, only one bit line pair is released from a precharge.equalize state to be connected to a corresponding sense amplifier in each bit line pair group in accordance with address information of the word line. Memory cells are arranged such that only one memory cell is connected to the selected word line in each bit line pair group.

    摘要翻译： 提供了一种半导体动态随机存取存储器，其包括被分成组和读出放大器的位线对，一行位于一行中的位线对的一侧上的位线对组。 当选择字线时，根据字线的地址信息，只有一个位线对从预充电状态被释放以连接到每个位线对组中的对应读出放大器。 存储单元被布置成使得在每个位线对组中只有一个存储单元连接到所选择的字线。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4730320A

    公开(公告)日：1988-03-08

    申请号：US825869

    申请日：1986-02-04

    申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Tsutomu Yoshihara

    发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Tsutomu Yoshihara

    IPC分类号： G06F11/10 ,  G06F11/267

    CPC分类号： G06F11/2215 ,  G06F11/1008 ,  G06F11/1076

    摘要： A semiconductor memory device comprises a data input switching circuit (20) connected between the output side of a write check bit generating circuit (2) and the input side of a check bit memory cell array (32), a data output switching circuit (30) connected to the input side of an address decoder (9), and an address switching circuit (10) connected to the output side of the address decoder (9). When a test mode is entered, the data input switching circuit (2), data output switching circuit (30) and address switching circuit (10) connect a data input signal line (l), data output signal line (m) and address signal line (n), respectively, to the check bit memory cell array (32), enabling the check bit memory cell array (32) to be accessed from the outside.

    摘要翻译： 半导体存储器件包括连接在写入校验位产生电路（2）的输出侧和校验位存储单元阵列（32）的输入侧之间的数据输入切换电路（20），数据输出切换电路（30） ）和连接到地址解码器（9）的输出侧的地址切换电路（10）。 当输入测试模式时，数据输入切换电路（2），数据输出切换电路（30）和地址切换电路（10）连接数据输入信号线（l），数据输出信号线（m）和地址信号 （n）分配给校验位存储单元阵列（32），从而能够从外部访问校验位存储单元阵列（32）。