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    Semiconductor memory device with address transition detection and timing control
    2.
    发明授权
    Semiconductor memory device with address transition detection and timing control 失效
    具有地址转换检测和定时控制的半导体存储器件

    公开(公告)号：US4843596A

    公开(公告)日：1989-06-27

    申请号：US124554

    申请日：1987-11-24

    申请人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

    发明人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

    IPC分类号： G11C11/401 ,  G11C7/22 ,  G11C8/18

    CPC分类号： G11C8/18 ,  G11C7/22

    摘要： A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.

    摘要翻译： 一种新颖的半导体存储器件包括响应于地址变化的检测而产生短宽度脉冲的地址检测电路。 列解码器激活信号发生器检测短宽度脉冲的开始，并且响应于产生列解码器激活信号。 第二检测电路检测短宽度脉冲的结论，并产生触发前置放大器激活信号的第二脉冲，其激活前置放大器并锁存输入/输出线上存在的数据。 复位信号发生器产生复位信号以停用列解码器激活信号并延迟前置放大器激活信号。 当输出第一个脉冲时，前置放大器激活信号发生器和复位信号发生器被复位。

    Block partitioned dynamic semiconductor memory device
    4.
    发明授权
    Block partitioned dynamic semiconductor memory device 失效
    块分割动态半导体存储器件

    公开(公告)号：US4934826A

    公开(公告)日：1990-06-19

    申请号：US211548

    申请日：1988-06-24

    申请人： Hideshi Miyatake ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Kazuhiro Tsukamoto

    发明人： Hideshi Miyatake ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Kazuhiro Tsukamoto

    IPC分类号： G11C11/406 ,  G11C11/408 ,  G11C11/409

    CPC分类号： G11C11/409 ,  G11C11/406 ,  G11C11/408

    摘要： A word line driving signal generating circuit and a sense amplifier activating signal generating circuit are provided for every partitioned memory cell array. When the levels of an external RAS signal and an external CAS signal have a predetermined relation and an external RNC signal remains at a predetermined potential or more, a refresh operation is started. A refresh address is generated from a refresh address counter in a sense restore control circuit. All of the memory cell arrays are simultaneously refreshed in response to the address. On this occasion, an operation for selecting a column by a column decoder provided in each of the memory cell arrays is inhibited. In the case in which an input of the external RNC signal is not prepared, when the levels of the external RAS signal and the external CAS signal have a predetermined relation and this state is held in a predetermined time period or more, the same refresh operation as described above is started.

    摘要翻译： 为每个分区存储单元阵列提供字线驱动信号发生电路和读出放大器激活信号产生电路。 当外部RAS信号和外部CAS信号的电平具有预定关系并且外部RNC信号保持在预定电位或更大时，开始刷新操作。 从感测恢复控制电路中的刷新地址计数器产生刷新地址。 响应于地址，所有的存储单元阵列被同时刷新。 在这种情况下，禁止通过设置在每个存储单元阵列中的列解码器来选择列的操作。 在没有准备外部RNC信号的输入的情况下，当外部RAS信号和外部CAS信号的电平具有预定关系并且该状态保持在预定时间段或更长时间时，相同的刷新操作 如上所述开始。

    Thiazole derivative and leukotriene antagonist containing the same as the effective ingredients
    5.
    发明授权
    Thiazole derivative and leukotriene antagonist containing the same as the effective ingredients 失效
    噻唑衍生物和含有与有效成分相同的白三烯拮抗剂

    公开(公告)号：US4902700A

    公开(公告)日：1990-02-20

    申请号：US279225

    申请日：1988-11-28

    申请人： Yosio Hayasi ,  Tomei Oguri ,  Masaki Shimoda ,  Mikio Tsutsui ,  Kazuo Takahashi ,  Hitoshi Miida

    发明人： Yosio Hayasi ,  Tomei Oguri ,  Masaki Shimoda ,  Mikio Tsutsui ,  Kazuo Takahashi ,  Hitoshi Miida

    IPC分类号： C07D417/12 ,  A61K31/425 ,  A61K31/426 ,  A61K31/428 ,  A61P37/08 ,  A61P43/00 ,  C07D277/20 ,  C07D277/22 ,  C07D277/24 ,  C07D277/28 ,  C07D277/30 ,  C07D277/56 ,  C07D277/64 ,  C07D277/82

    CPC分类号： C07D277/82 ,  C07D277/24 ,  C07D277/28 ,  C07D277/30 ,  C07D277/56 ,  C07D277/64

    摘要： Disclosed are a thiazole derivative represented by the following formula, a pharmaceutically acceptable salt thereof and leukotriene antagonist containing the same as the active ingredients: ##STR1## wherein R.sub.1 and R.sub.2 each independently represent a hydrogen atom, an alkyl group having 1 to 8 carbon atoms, a lower alkoxycarbonyl group or a substituted or unsubstituted phenyl group or cooperatively represent a tetramethylene group corresponding to a fused cyclohexane ring or a butadienylene group which is unsubstituted or substituted with a halogen atom, a lower alkoxy group, a lower alkoxycarbonyl group or an alkyl group having 1 to 3 carbon atoms corresponding to a fused benzene ring; R.sub.3, R.sub.4, R.sub.5 and R.sub.6 each independently represent a hydrogen atom, a hydroxyl group, a lower alkoxy group, an alkyl group having 1 to 3 carbon atoms or a halogen atom; A represents a linking group having 2 to 4 chain members; B represents a linking group having 2 to 5 chain members; and Q represents a carboxyl group, a lower alkoxy group, a hydroxyl group, an alkoxycarbonyl group having 2 to 6 carbon atoms or a 5-tetrazolyl group.

    摘要翻译： 公开了由下式表示的噻唑衍生物，其药学上可接受的盐和含有与活性成分相同的白三烯拮抗剂：其中R 1和R 2各自独立地表示氢原子，具有1至8个碳原子的烷基 低级烷氧基羰基或取代或未取代的苯基，或协同表示对应于未被取代或被卤素原子，低级烷氧基，低级烷氧基羰基或烷基取代的稠环己烷环或丁二烯基的四亚甲基 对应于稠合苯环的具有1至3个碳原子的基团; R 3，R 4，R 5和R 6各自独立地表示氢原子，羟基，低级烷氧基，碳原子数1〜3的烷基或卤素原子。 A表示具有2至4个链成员的连接基团; B表示具有2至5个链成员的连接基团; Q表示羧基，低级烷氧基，羟基，碳原子数2〜6的烷氧基羰基或5-四唑基。

    Slew rate adjusting circuit and semiconductor device
    6.
    发明授权
    Slew rate adjusting circuit and semiconductor device 失效

    公开(公告)号：US06518808B2

    公开(公告)日：2003-02-11

    申请号：US09871738

    申请日：2001-06-04

    申请人： Masaki Shimoda

    发明人： Masaki Shimoda

    IPC分类号： H03B100

    CPC分类号： H03K17/164 ,  H03K5/135

    摘要： In a slew rate adjusting circuit for producing a timing signal determining an output slew rate, a delay circuit for producing an output timing signal is formed of delay circuits with a variable number of delay stages, and the delay time of the output timing signal is adjusted in a step of a delay time of the delay stage in accordance with slew rate adjusting data. A large adjustment margin can be ensured for the output slew rate determining the changing rate of the output data.

    Super VCC detection circuit
    7.
    发明授权
    Super VCC detection circuit 失效
    超级VCC检测电路

    公开(公告)号：US5578942A

    公开(公告)日：1996-11-26

    申请号：US487212

    申请日：1995-06-07

    申请人： Masaki Shimoda ,  Yoshinori Inoue

    发明人： Masaki Shimoda ,  Yoshinori Inoue

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C5/14 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/46 ,  G11C29/50 ,  H03K17/16

    CPC分类号： G11C5/147 ,  G11C29/46 ,  G11C5/143 ,  G11C7/1045

    摘要： A transfer gate is provided between an input terminal, receiving voltage Vh of the super Vcc level when a special operating mode is set, and an inverter and an n channel MOS transistor included in a super Vcc detection circuit of a DRAM. The transfer gate is rendered conductive only during a potential detection period during which signal WCBR attain an "H" level. Therefore, a leakage current flowing from the input terminal through the n channel MOS transistor to a ground terminal can be minimized, thereby reducing a consumed current.

    摘要翻译： 在设置特殊工作模式时，在输入端子，超级电容器级别的接收电压Vh与包含在DRAM的超级Vcc检测电路中的反相器和n沟道MOS晶体管之间提供传输门。 传输门仅在信号WCBR达到“H”电平的电势检测期间内导通。 因此，从输入端子通过n沟道MOS晶体管流到接地端子的漏电流可以最小化，从而减少消耗的电流。

    Semiconductor memory device with shortened connection length among memory block, data buffer and data bus
    8.
    发明授权
    Semiconductor memory device with shortened connection length among memory block, data buffer and data bus 有权
    具有缩短存储块，数据缓冲器和数据总线之间连接长度的半导体存储器件

    公开(公告)号：US06787859B2

    公开(公告)日：2004-09-07

    申请号：US10223319

    申请日：2002-08-20

    申请人： Takashi Itou ,  Masaki Shimoda ,  Yasuhiko Tsukikawa

    发明人： Takashi Itou ,  Masaki Shimoda ,  Yasuhiko Tsukikawa

    IPC分类号： H01L2994

    CPC分类号： G11C5/025 ,  G11C7/18

    摘要： There is provided a semiconductor memory device including eight memory blocks 20a to 20h, first data bus 22a, and second data bus 22b. The eight memory blocks are arranged at respective eight of the total nine areas 11 to 19 defined in a three rows by three columns matrix except for a center area 19. A first data bus 22a linearly extends between memory blocks in the first and second row of the matrix. A second data bus 22b linearly extends between memory blocks in the second and third row of the matrix. The eight memory blocks includes a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus.

    摘要翻译： 提供了包括八个存储块20a至20h，第一数据总线22a和第二数据总线22b的半导体存储器件。 八个存储块被布置在除了中心区域19之外以三行×三列矩阵定义的总共九个区域11至19中的相应八个。第一数据总线22a在第一和第二行中的存储块之间线性地延伸 矩阵。 第二数据总线22b在矩阵的第二和第三行中的存储块之间线性地延伸。 八个存储器块包括与第一数据总线相邻布置并连接到第一数据总线的四个存储器块的第一组以及与第二数据总线相邻布置并连接到第二数据总线的四个存储器块的第二组。

    Semiconductor memory device having a plurality of I/O terminal groups
    10.
    发明授权
    Semiconductor memory device having a plurality of I/O terminal groups 失效
    具有多个I / O端子组的半导体存储器件

    公开(公告)号：US5623447A

    公开(公告)日：1997-04-22

    申请号：US597822

    申请日：1996-02-07

    申请人： Masaki Shimoda

    发明人： Masaki Shimoda

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/1057 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/108

    摘要： There are provided upper and lower data I/O terminal groups, each forming a unit for input/output of data. When an early write detecting circuit included in a clock generating circuit detects designation of an early write mode and one of the groups is designated for writing, lower or upper input buffers controlled by write control circuit takes in the data. Concurrently, in response to the detection of mode, lower or upper output buffer uses, for reading, the other group not taking in data for writing. In this mode, therefore, the write and read operations are executed simultaneously. Thereby, simultaneous operation of the write and read data is allowed, and a data processing speed is improved.

    摘要翻译： 提供了上下数据I / O端子组，每个组成一个单元，用于输入/输出数据。 当包括在时钟发生电路中的早期写入检测电路检测到早期写入模式的指定并且指定组中的一个写入时，由写入控制电路控制的下部或上部输入缓冲器接收数据。 同时，响应于模式的检测，较低或较高的输出缓冲器用于读取另一组不接收数据进行写入。 因此，在该模式中，同时执行写入和读取操作。 从而，允许写入和读取数据的同时操作，并且提高数据处理速度。