In a semiconductor integrated circuit such as a semiconductor memory device capable of operating in a special mode in addition to a standard operation mode, a high voltage detection circuit 10 detects a high voltage applied to one of control signal input terminals CS and outputs a detection signal HV to a special mode circuit 14. The special mode circuit 14 outputs a switch signal CO to a switching circuit 11 in response to the detection signal HV. The switching circuit 11 connects an input/output buffer 7 to a latch circuit 12 in response to the switch signal CO. A special mode code MC is applied to input/output terminals DT and transmitted to the latch circuit 12 through the switching circuit 11. A special mode decoder 13 decodes the special mode code MC which has been latched by the latch circuit 12 and outputs a signal for specifying the special mode to a control circuit 8. Operation in the special mode specified by the control circuit 8 is executed. By detecting a confirmation signal CS applied to one of the control signal input terminals CS during the execution of the special mode, the special mode code MC which has been already latched by the latch circuit 12 can be outputted from the input/output terminals DT.