发明授权
- 专利标题: Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing
- 专利标题(中): 使用低熔点无机材料平面化集成电路结构并在沉积时流动的方法
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申请号: US644853申请日: 1991-01-22
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公开(公告)号: US5112776A公开(公告)日: 1992-05-12
- 发明人: Jeffrey Marks , Kam S. Law , David N. Wang , Dan Mayden
- 申请人: Jeffrey Marks , Kam S. Law , David N. Wang , Dan Mayden
- 申请人地址: CA Santa Clara
- 专利权人: Applied Materials, Inc.
- 当前专利权人: Applied Materials, Inc.
- 当前专利权人地址: CA Santa Clara
- 主分类号: H01L21/3105
- IPC分类号: H01L21/3105 ; H01L21/316 ; H01L21/768
摘要:
A planarizing process is disclosed for planarizing an integrated circuit structure using a low melting inorganic planarizing material which comprises flowing while depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon and then dry etching the low melting inorganic planarizing layer to planarize the structure. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are carried out without removing the integrated circuit structure from the vacuum apparatus. An additional etching step may be carried out after depositing the insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.
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