发明授权
- 专利标题: Current mirror circuit employing depletion mode FETs
- 专利标题(中): 采用耗尽型FET的电流镜电路
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申请号: US364461申请日: 1989-06-12
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公开(公告)号: US5166553A公开(公告)日: 1992-11-24
- 发明人: Nobuo Kotera , Kiichi Yamashita , Hirotoshi Tanaka , Satoshi Tanaka , Yasushi Hatta , Minoru Nagata
- 申请人: Nobuo Kotera , Kiichi Yamashita , Hirotoshi Tanaka , Satoshi Tanaka , Yasushi Hatta , Minoru Nagata
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX63-150282 19880620
- 主分类号: G05F3/24
- IPC分类号: G05F3/24 ; G05F3/26 ; H03F3/34 ; H03F3/343 ; H03F3/347 ; H03K17/14
摘要:
A semiconductor circuit including first and second FET's for delivering an output signal without being affected by a change in threshold voltage of the FET's is disclosed. According to one practical form of the semiconductor circuit, the drain-source current path of an additional FET whose gate and source are shorted to each other, is connected in parallel to the drain-source current path of the first FET whose gate and drain are shorted to each other, to make the voltage-current characteristic of the second FET agree with that of the parallel combination of the first and additional FET's. According to another practical form of the semiconductor circuit, a voltage dividing circuit is connected in parallel to the drain-source current path of the first FET, and a divided output voltage from the voltage dividing circuit is applied between the gate and source of each of the first and second FET's.
公开/授权文献
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