发明授权
US5218219A Semiconductor memory device having a peripheral wall at the boundary
region of a memory cell array region and a peripheral circuit region
失效
在存储器单元区域和外围电路区域的边界区域具有外围壁的半导体存储器件
- 专利标题： Semiconductor memory device having a peripheral wall at the boundary region of a memory cell array region and a peripheral circuit region
- 专利标题（中）： 在存储器单元区域和外围电路区域的边界区域具有外围壁的半导体存储器件
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申请号： US678872申请日： 1991-04-04
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公开(公告)号： US5218219A公开(公告)日： 1993-06-08
- 发明人: Natsuo Ajika , Hideaki Arima , Kaoru Motonami , Atsushi Hachisuka , Tomonori Okudaira
- 申请人： Natsuo Ajika , Hideaki Arima , Kaoru Motonami , Atsushi Hachisuka , Tomonori Okudaira
- 申请人地址： JPX Tokyo
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX2-113633 19900427
- 主分类号： H01L27/10
- IPC分类号： H01L27/10 ; H01L21/8242 ; H01L27/108
摘要：
A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.
公开/授权文献
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