公开(公告)号：US5218219A

公开(公告)日：1993-06-08

申请号：US678872

申请日：1991-04-04

申请人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10817

摘要： A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.

摘要翻译： 公开了一种动态随机存取存储器（DRAM），其即使在高集成器件中也能够有效地防止存储单元阵列101和外围电路102的边界区域中的步骤的形成。 该DRAM包括在存储单元阵列101的边界区域和P型硅衬底1的外围电路102的外围壁20a和20b的双周壁20，P型硅衬底1从P型硅衬底1垂直向上延伸。 形成在存储单元阵列上的器件的表面和外围电路102在存储单元阵列101和外围电路102上的形成装置中通过双周壁20的病毒基本平坦化，从而有效地防止了在步骤 存储单元阵列101和外围电路102的边界区域，即使在高集成器件中。

公开(公告)号：US5364811A

公开(公告)日：1994-11-15

申请号：US17901

申请日：1993-02-16

申请人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10817

摘要： A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.

摘要翻译： 公开了一种动态随机存取存储器（DRAM），其即使在高集成器件中也能够有效地防止存储单元阵列101和外围电路102的边界区域中的步骤的形成。 该DRAM包括在存储单元阵列101的边界区域和P型硅衬底1的外围电路102的外围壁20a和20b的双周壁20，P型硅衬底1从P型硅衬底1垂直向上延伸。 形成在存储单元阵列上的器件的表面和外围电路102在存储单元阵列101和外围电路102上的形成装置中通过双周壁20的病毒基本平坦化，从而有效地防止了在步骤 存储单元阵列101和外围电路102的边界区域，即使在高集成器件中。

公开(公告)号：US5672533A

公开(公告)日：1997-09-30

申请号：US555414

申请日：1995-11-09

申请人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L21/8242 ,  H01L29/68 ,  H01L29/76 ,  H01L29/78 ,  H01L29/92 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L27/1085 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/66659

摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.

摘要翻译： 公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。 半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区， 电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。 因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。

公开(公告)号：US5489791A

公开(公告)日：1996-02-06

申请号：US100950

申请日：1993-08-03

申请人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L21/8242 ,  H01L29/68 ,  H01L29/76 ,  H01L29/78 ,  H01L29/92 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L27/1085 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/66659

摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.

摘要翻译： 公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。 半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区， 电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。 因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。

公开(公告)号：US5276344A

公开(公告)日：1994-01-04

申请号：US13500

申请日：1993-02-02

申请人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L21/8242 ,  H01L29/68 ,  H01L29/76 ,  H01L29/78 ,  H01L29/92 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L27/1085 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/66659

摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.

摘要翻译： 公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。 半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区， 电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。 因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。

公开(公告)号：US5229314A

公开(公告)日：1993-07-20

申请号：US925153

申请日：1992-08-06

申请人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

发明人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41775 ,  H01L27/10817 ,  H01L29/7831

摘要： A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.

摘要翻译： 公开了一种场效应晶体管及其制造方法，即使在缩小到更高的集成度时，也不会降低多层互连层之间的耐电压特性。 该场效应晶体管包括形成在位线15两侧的侧壁21a，使得底侧端接触栅电极4b和4c的侧壁20a的上表面。 插入在栅电极4b和4c之间的绝缘膜的厚度和形成电容器的低电极11的基部11a的厚度不降低。 即使缩放到更高的集成度，耐压电压的特性也不会在多层互连层之间劣化。

公开(公告)号：US5157469A

公开(公告)日：1992-10-20

申请号：US685398

申请日：1991-04-16

申请人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

发明人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

IPC分类号： H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41775 ,  H01L27/10817 ,  H01L29/7831 ,  Y10S257/90

摘要： A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.

摘要翻译： 公开了一种场效应晶体管及其制造方法，即使在缩小到更高的集成度时，也不会降低多层互连层之间的耐电压特性。 该场效应晶体管包括形成在位线15两侧的侧壁21a，使得底侧端接触栅电极4b和4c的侧壁20a的上表面。 插入在栅电极4b和4c之间的绝缘膜的厚度和形成电容器的低电极11的基部11a的厚度不降低。 即使缩放到更高的集成度，耐压电压的特性也不会在多层互连层之间劣化。

公开(公告)号：US5453952A

公开(公告)日：1995-09-26

申请号：US869937

申请日：1992-04-17

申请人： Tomonori Okudaira ,  Kaoru Motonami

发明人： Tomonori Okudaira ,  Kaoru Motonami

IPC分类号： G11C11/401 ,  H01L21/768 ,  H01L21/822 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78

CPC分类号： H01L27/1203 ,  H01L27/0688 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/10808

摘要： A semiconductor device having an increased integration density. The semiconductor device includes a memory cell array, and a peripheral circuit region formed over the memory cell array and to be in electrical connection to the memory cell array for controlling the input/output of the data signals. A large part of a semiconductor chip area can therefore be used for the memory cell array, thereby increasing the integration density of the semiconductor device.

摘要翻译： 具有增加的集成密度的半导体器件。 半导体器件包括存储单元阵列和形成在存储单元阵列上并与存储单元阵列电连接的外围电路区域，用于控制数据信号的输入/输出。 因此，可以将半导体芯片面积的大部分用于存储单元阵列，从而提高半导体器件的集成密度。

公开(公告)号：US5428239A

公开(公告)日：1995-06-27

申请号：US71023

申请日：1993-06-03

申请人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

发明人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

IPC分类号： H01L27/10 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/823892 ,  H01L21/76221 ,  H01L21/823493 ,  H01L27/10805 ,  H01L27/0928 ,  H01L27/105

摘要： A DRAM is formed on a silicon substrate having a retrograde well and a diffusion-type well. The retrograde well has an impurity concentration profile which is set in steps by a plurality of ion-implantations. The diffusion-type well has an impurity concentration profile which changes monotonously by a thermal diffusion. A memory cell array is formed in the retrograde well region. A peripheral circuit is formed in the diffusion-type well region. The retrograde well enhances integration of devices included in the memory cell array. The diffusion-type well enhances the characteristic of insulating isolation between devices.

摘要翻译： 在具有逆行阱和扩散型阱的硅衬底上形成DRAM。 逆行井具有通过多个离子注入步骤设置的杂质浓度分布。 扩散型阱具有通过热扩散单调变化的杂质浓度分布。 在逆行井区域中形成记忆单元阵列。 在扩散型阱区域中形成外围电路。 逆行井增强了存储单元阵列中包含的器件的集成。 扩散型井增强了器件之间绝缘隔离的特性。

公开(公告)号：US5404042A

公开(公告)日：1995-04-04

申请号：US71925

申请日：1993-06-04

申请人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

发明人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L49/00 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/10805 ,  H01L27/0218 ,  H01L27/105

摘要： A semiconductor memory device in accordance with the present invention includes a plurality of n well regions and p well regions in a p type silicon substrate. One of the p well regions is connected to an external power supply. Peripheries of the p well region having a memory cell array formed therein are surrounded by an n well region having a potential held at a positive potential. The n well region held at the positive potential prevents electrons introduced into the substrate due to undershoot from entering into a p well region through the p well region connected to the external power supply.

摘要翻译： 根据本发明的半导体存储器件包括p型硅衬底中的多个n阱区和p阱区。 p个阱区中的一个连接到外部电源。 具有其中形成有存储单元阵列的p阱区的周边被具有保持在正电位的电位的n阱区围绕。 保持在正电位的n阱区防止由于下冲通过连接到外部电源的p阱区进入p阱区而引入到衬底中的电子。