公开(公告)号：US5218219A

公开(公告)日：1993-06-08

申请号：US678872

申请日：1991-04-04

申请人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10817

摘要： A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.

摘要翻译： 公开了一种动态随机存取存储器（DRAM），其即使在高集成器件中也能够有效地防止存储单元阵列101和外围电路102的边界区域中的步骤的形成。 该DRAM包括在存储单元阵列101的边界区域和P型硅衬底1的外围电路102的外围壁20a和20b的双周壁20，P型硅衬底1从P型硅衬底1垂直向上延伸。 形成在存储单元阵列上的器件的表面和外围电路102在存储单元阵列101和外围电路102上的形成装置中通过双周壁20的病毒基本平坦化，从而有效地防止了在步骤 存储单元阵列101和外围电路102的边界区域，即使在高集成器件中。

公开(公告)号：US5364811A

公开(公告)日：1994-11-15

申请号：US17901

申请日：1993-02-16

申请人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10817

摘要： A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.

摘要翻译： 公开了一种动态随机存取存储器（DRAM），其即使在高集成器件中也能够有效地防止存储单元阵列101和外围电路102的边界区域中的步骤的形成。 该DRAM包括在存储单元阵列101的边界区域和P型硅衬底1的外围电路102的外围壁20a和20b的双周壁20，P型硅衬底1从P型硅衬底1垂直向上延伸。 形成在存储单元阵列上的器件的表面和外围电路102在存储单元阵列101和外围电路102上的形成装置中通过双周壁20的病毒基本平坦化，从而有效地防止了在步骤 存储单元阵列101和外围电路102的边界区域，即使在高集成器件中。

公开(公告)号：US5173752A

公开(公告)日：1992-12-22

申请号：US690824

申请日：1991-04-26

申请人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

发明人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L27/10817 ,  H01L2924/0002 ,  Y10S257/90

摘要： A semiconductor device incloudes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

摘要翻译： 半导体器件包括MOS型场效应晶体管，其栅电极（4）的表面被第一绝缘膜（5）覆盖，左侧和右侧设置有一对第二绝缘膜（10）。 第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面 （4）。 至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。 在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。 该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

公开(公告)号：US5240872A

公开(公告)日：1993-08-31

申请号：US925148

申请日：1992-08-06

申请人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

发明人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

IPC分类号： H01L21/8242 ,  H01L23/485 ,  H01L27/108

CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L27/10817 ,  H01L2924/0002

摘要： A semiconductor device includes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

摘要翻译： 半导体器件包括MOS型场效应晶体管，其栅极（4）的表面被第一绝缘膜（5）覆盖，左右侧设置有一对第二绝缘膜（10）。 第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面 （4）。 至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。 在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。 该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

公开(公告)号：US5229314A

公开(公告)日：1993-07-20

申请号：US925153

申请日：1992-08-06

申请人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

发明人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41775 ,  H01L27/10817 ,  H01L29/7831

摘要： A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.

摘要翻译： 公开了一种场效应晶体管及其制造方法，即使在缩小到更高的集成度时，也不会降低多层互连层之间的耐电压特性。 该场效应晶体管包括形成在位线15两侧的侧壁21a，使得底侧端接触栅电极4b和4c的侧壁20a的上表面。 插入在栅电极4b和4c之间的绝缘膜的厚度和形成电容器的低电极11的基部11a的厚度不降低。 即使缩放到更高的集成度，耐压电压的特性也不会在多层互连层之间劣化。

公开(公告)号：US5157469A

公开(公告)日：1992-10-20

申请号：US685398

申请日：1991-04-16

申请人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

发明人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

IPC分类号： H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41775 ,  H01L27/10817 ,  H01L29/7831 ,  Y10S257/90

摘要： A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.

摘要翻译： 公开了一种场效应晶体管及其制造方法，即使在缩小到更高的集成度时，也不会降低多层互连层之间的耐电压特性。 该场效应晶体管包括形成在位线15两侧的侧壁21a，使得底侧端接触栅电极4b和4c的侧壁20a的上表面。 插入在栅电极4b和4c之间的绝缘膜的厚度和形成电容器的低电极11的基部11a的厚度不降低。 即使缩放到更高的集成度，耐压电压的特性也不会在多层互连层之间劣化。

公开(公告)号：US5453952A

公开(公告)日：1995-09-26

申请号：US869937

申请日：1992-04-17

申请人： Tomonori Okudaira ,  Kaoru Motonami

发明人： Tomonori Okudaira ,  Kaoru Motonami

IPC分类号： G11C11/401 ,  H01L21/768 ,  H01L21/822 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78

CPC分类号： H01L27/1203 ,  H01L27/0688 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/10808

摘要： A semiconductor device having an increased integration density. The semiconductor device includes a memory cell array, and a peripheral circuit region formed over the memory cell array and to be in electrical connection to the memory cell array for controlling the input/output of the data signals. A large part of a semiconductor chip area can therefore be used for the memory cell array, thereby increasing the integration density of the semiconductor device.

摘要翻译： 具有增加的集成密度的半导体器件。 半导体器件包括存储单元阵列和形成在存储单元阵列上并与存储单元阵列电连接的外围电路区域，用于控制数据信号的输入/输出。 因此，可以将半导体芯片面积的大部分用于存储单元阵列，从而提高半导体器件的集成密度。

公开(公告)号：US20080135909A1

公开(公告)日：2008-06-12

申请号：US11948377

申请日：2007-11-30

申请人： Toru Takeguchi ,  Takuji Imamura ,  Kazushi Yamayoshi ,  Tomoyuki Irizumi ,  Atsunori Nishiura ,  Kaoru Motonami

发明人： Toru Takeguchi ,  Takuji Imamura ,  Kazushi Yamayoshi ,  Tomoyuki Irizumi ,  Atsunori Nishiura ,  Kaoru Motonami

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L28/60 ,  G02F1/136213 ,  G02F1/136227 ,  H01L27/1255 ,  H01L27/1288

摘要： In a thin film transistor using a polycrystalline semiconductor film, when a storage capacitor is formed, it is often that a polycrystalline semiconductor film is used also in one electrode of the capacity. In a display device having a storage capacitor and thin film transistor which have a polycrystalline semiconductor film, the storage capacitor exhibits a voltage dependency due to the semiconductor film, and hence a display failure is caused. In the display device of the invention, a metal conductive film 5 is stacked above a semiconductor layer 4d made of a polycrystalline semiconductor film which is used as a lower electrode of a storage capacitor 130.

摘要翻译： 在使用多晶半导体膜的薄膜晶体管中，当形成存储电容时，通常多晶半导体膜也用于一个容量的电极中。 在具有具有多晶半导体膜的存储电容器和薄膜晶体管的显示装置中，存储电容器由于半导体膜而呈现电压依赖性，因此导致显示不良。 在本发明的显示装置中，金属导电膜5层叠在用作保持电容器130的下电极的多晶半导体膜的半导体层4d的上方。

公开(公告)号：US20070200111A1

公开(公告)日：2007-08-30

申请号：US11624419

申请日：2007-01-18

申请人： Yasuyoshi Itoh ,  Kaoru Motonami

发明人： Yasuyoshi Itoh ,  Kaoru Motonami

IPC分类号： H01L29/04

CPC分类号： G02F1/133553 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136286 ,  G02F2001/136231

摘要： An additional circuit is formed on a glass substrate, and a passivation film is deposited thereon. After an insulation film is deposited on the passivation film, a contact hole is formed, and a signal line is deposited and connected to the additional circuit. After the signal line and the insulation film are patterned, an organic insulation film is formed, to thereby have a surface of an uneven configuration depending on a step formed by the signal line and the insulation film. A reflective electrode is formed on the organic insulation film, to thereby have a surface of an uneven configuration. This eliminates the need to perform a photolithography process step for the formation of the surface of the organic insulation film in the uneven configuration, thereby reducing manufacturing costs.

摘要翻译： 在玻璃基板上形成附加电路，并在其上沉积钝化膜。 在绝缘膜沉积在钝化膜上之后，形成接触孔，并且将信号线沉积并连接到附加电路。 在信号线和绝缘膜被图案化之后，形成有机绝缘膜，从而具有取决于由信号线和绝缘膜形成的台阶的不平坦构造的表面。 反射电极形成在有机绝缘膜上，从而具有凹凸形状的表面。 因此，不需要进行用于形成不均匀构造的有机绝缘膜的表面的光刻工序，从而降低制造成本。

公开(公告)号：US5962907A

公开(公告)日：1999-10-05

申请号：US967614

申请日：1997-11-10

申请人： Kaoru Motonami

发明人： Kaoru Motonami

IPC分类号： H01L21/8234 ,  H01L21/82 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L29/00 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/105 ,  H01L27/1052

摘要： A semiconductor device having a memory device and a logic device formed together on a single chip is provided. A first element region and a second element region of a semiconductor substrate are formed spaced apart from each other with an isolation region therebetween. A floating conductive film is provided on the isolation region.

摘要翻译： 提供了具有在单个芯片上一起形成的存储器件和逻辑器件的半导体器件。 半导体衬底的第一元件区域和第二元件区域之间具有隔离区域形成为彼此间隔开。 在隔离区域上设置浮置导电膜。