In a semiconductor memory device having memory cells (21.sub.i, 21.sub.i+1) disposed at intersections of bit lines (BL, BL) and word lines (WL.sub.i, WL.sub.i+1) and operating on an internal power source voltage (V.sub.D) which is lower than an external power source voltage for the memory device, sense amplifiers (41) are activated by a voltage on a drive common node (NS), and a comparator (110) is activated by the control signal (PAS) and compares the voltage on the common node (PS) with the internal power source voltage (V.sub.D). The comparator has an output which is in a first state when the common node (PS) voltage is not higher than the reference voltage (V.sub.R) and which is in a second state when the common node (PS) voltage exceeds the reference voltage (V.sub.R). A latch circuit (120) is turned from a first state to a second state when the control signal (PAS) is turned active, thereby to activate the comparator (110) and a power source supply circuit (130, 132) which then supplies a drive voltage to the common node (PS). The latch circuit is turned from the first state to the second state when the output of the comparator (110) is turned to the second state. The latch circuit deactivates the comparator (110) when it is turned to the first state.