- 专利标题: Semiconductor memory device
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申请号: US849458申请日: 1992-03-11
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公开(公告)号: US5258957A公开(公告)日: 1993-11-02
- 发明人: Katsuhiro Seta , Hiroyuki Hara , Takayasu Sakurai , Yoshinori Watanabe
- 申请人: Katsuhiro Seta , Hiroyuki Hara , Takayasu Sakurai , Yoshinori Watanabe
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX3-049673 19910314
- 主分类号: G11C11/41
- IPC分类号: G11C11/41 ; G11C7/06 ; G11C7/18 ; G11C11/401 ; G11C11/414 ; G11C13/00
摘要:
In a semiconductor memory device of a divided bit line system, read signals from memory cell blocks are sense-amplified together by a single differential bit line sense amplifier. The bit line sense amplifier includes a plurality of first transistors, the base electrodes of which are connected to local bit lines of the memory cell blocks, the emitter electrodes of which are commonly connected to corresponding main bit lines, and the collector electrodes of which are connected to a first power supply node, a second transistor, which forms a differential pair with each of the first transistors, the base electrode of which is applied with a reference bias potential, and the emitter electrode of which is connected to the main bit lines, a current source connected between the emitter electrode of the second transistor, and a second power supply node, and a load circuit connected between the collector electrode of the second transistor and the first power supply node. The main bit lines with a heavy load can be driven by the emitters having a large driving force, and the outputs from the memory cell blocks can be sensed without going through selectors, thus attaining high-speed read access.