摘要:
In a semiconductor memory device of a divided bit line system, read signals from memory cell blocks are sense-amplified together by a single differential bit line sense amplifier. The bit line sense amplifier includes a plurality of first transistors, the base electrodes of which are connected to local bit lines of the memory cell blocks, the emitter electrodes of which are commonly connected to corresponding main bit lines, and the collector electrodes of which are connected to a first power supply node, a second transistor, which forms a differential pair with each of the first transistors, the base electrode of which is applied with a reference bias potential, and the emitter electrode of which is connected to the main bit lines, a current source connected between the emitter electrode of the second transistor, and a second power supply node, and a load circuit connected between the collector electrode of the second transistor and the first power supply node. The main bit lines with a heavy load can be driven by the emitters having a large driving force, and the outputs from the memory cell blocks can be sensed without going through selectors, thus attaining high-speed read access.
摘要:
An ECL output buffer circuit is constituted by an output buffer circuit main portion and its control circuit. In the output buffer circuit main portion, an output from a differential switch is input to the base of a bipolar transistor (emitter follower). The emitter of the bipolar transistor is connected to an output terminal. A ground potential is applied to the collector of the bipolar transistor. One end of the channel conductive path of a MOS transistor is connected to the base of the bipolar transistor. The other end of the channel conductive path is connected to a power-supply terminal via a constant-current source. The control circuit controls the ON/OFF operation of the MOS transistor and the output level of the bipolar transistor. When the output buffer circuit main portion is to be set in a standby state, the control circuit performs control to set the MOS transistor in an ON state and set the output of the bipolar transistor at low level.
摘要:
A full adder circuit has a plurality of full adders each provided for each bit. Each full adder has: a calculation block (31a) responsive to a first carry signal (C) given by a preceding stage bit as a differential signal and two external input data (A1, B1) to be added at a present stage bit, for outputting addition data calculated on the basis of the first carry signal and the external input data as two differential signals, and further outputting a second carry signal (/C) to a succeeding bit as a differential signal indicative of whether a carry is generated by the present stage bit or not. Each full adder also has a latch type sense amplifier (16a) for outputting an addition result (SUM) of the present stage bit, after having differentially amplified and latched the addition data outputted by the calculation block. Since the addition operation is made on the basis of the carry signals (C and /C) of a minute potential difference (before amplification), it is possible to shorten the required charging time and to reduce the current consumption. In addition, since the sense amplifiers (16a) are provided with the latch function (18a), it is possible to control the differential amplification operation and the latch operation on the basis of a common sense amplifier activating signal (SAB), so that the number of elements can be reduced.
摘要:
The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.
摘要:
A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is connected to each word line and each power supply line. In accessing the plurality of memory cells row by row, the control circuit raises the voltage of the power supply line and, after the voltage of the power supply line reaches the high voltage at all the positions, starts activation of the word line. On the other hand, in turning from the access state to the non-access state, the control circuit deactivates the word line and, after the voltage of the word line changes to the ground voltage at all the positions, changes the voltage of the power supply line to the low voltage.
摘要:
A semiconductor memory device includes a first memory cell array and a second memory cell array section into which the same data can be simultaneously written. Logic gates are provided between the word lines of the first memory cell array section and the respective word lines of the second memory cell array section. In the normal operation mode, the logic gates connect each of the rows of memory cells in the first memory cell array section to a corresponding one of the rows of memory cells in the second memory cell array section, and set each of the rows of memory cells in the second memory cell array section to a selected level when the same data is simultaneously written into the memory cells of the second memory cell array section. When each of the rows of memory cells in the second memory cell array section is set to the selected level, all the columns of the memory cells in the second memory cell array section are simultaneously selected and the same data is simultaneously written into the second memory cell array section.
摘要:
A semiconductor memory device includes a memory cell array, a spare memory cell array, a first addressing circuit for designating an address of the memory cell array, a second addressing circuit for designating an address of the spare memory cell array, a drive circuit for activating a select line designated by each of the first and second addressing circuits, a program circuit for generating a predetermined output based on whether the memory cell array has a defect or fault or not, and a select circuit responsive to an output from the program circuit for supplying an activation signal to the designated select line at an earlier timing when there is no fault in the memory array cell, and supplying an activation signal delayed by a time necessary for the selection of the spare memory cell array when there is a fault in the memory cell array.
摘要:
An MOS semiconductor circuit includes cascade connected logical circuits. The MOS semiconductor circuit further includes an MOS transistor circuit having at least one first MOS transistor coupled between a source voltage terminal and the output node of the individual logical circuits, and a second MOS transistor, which has the same conductivity type as the first MOS transistor and has its gate and drain short-circuited, with this gate being coupled to the gate of the first MOS transistor. The MOS semiconductor circuit also includes a current control circuit, which is coupled to the drain of the second MOS transistor for providing a predetermined current between the source and drain of the second MOS transistor.
摘要:
This invention provides an intermediate potential generating circuit comprising a load element of which one end is connected to a first potential supply source, a first transistor of a first conductivity type of which one end and the gate thereof are connected to the other end of the load element, a second transistor of a second conductivity type of which one end is connected to the other end of the first transistor, and the gate and the other end thereof are connected together, a constant-voltage means connected between the other end of the second transistor and a second potential supply source for causing a specific voltage drop between the ends of the contant-voltage means, a third transistor of the first conductivity type of which one end is connected to the first potential supply source, the gate is connected to a node between the load element and the first transistor, and the other end thereof is connected to an output terminal, and a fourth transistor of the second conductivity type which is connected between the output terminal and the second supply source and of which the gate is connected to a node between the second transistor and the constant-voltage means.
摘要:
The semiconductor memory device contains a plurality of memory cells, a row decoder for selectively actuating memory cells according to the selected one of the row and column address signals, and bit lines set to a potential dependent on the data in the memory cell actuated. Particularly, this memory device has latching circuits for latching the potentials on the bit lines, and a timing controller for causing the latching circuits to keep the latched potentials for a predetermined period after the update of the row address signal.