发明授权
US5373469A Differential amplifier with a latching function and a memory apparatus employing same 失效
具有锁存功能的差分放大器和采用该功能的存储装置

Differential amplifier with a latching function and a memory apparatus
employing same
摘要:
A high-speed memory employing the pipeline technique is disclosed, in which the minimum operating cycle time is reduced by use of a latch circuit for a small signal using a bipolar transistor. A small-signal latch circuit operating at a signal smaller than an output signal level is inserted between an amplifier circuit for amplifying the data held in a memory cell circuit and an output buffer circuit. A switch signal is also interposed between the latch circuit and the amplifier circuit, thereby shortening the cycle time.
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