发明授权
US5373469A Differential amplifier with a latching function and a memory apparatus
employing same
失效
具有锁存功能的差分放大器和采用该功能的存储装置
- 专利标题: Differential amplifier with a latching function and a memory apparatus employing same
- 专利标题(中): 具有锁存功能的差分放大器和采用该功能的存储装置
-
申请号: US890260申请日: 1992-05-29
-
公开(公告)号: US5373469A公开(公告)日: 1994-12-13
- 发明人: Takashi Akioka , Noboru Akiyama , Yutaka Kobayashi , Tatsuyuki Ohta , Koyo Katsura
- 申请人: Takashi Akioka , Noboru Akiyama , Yutaka Kobayashi , Tatsuyuki Ohta , Koyo Katsura
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX3-129050 19910531
- 主分类号: G11C11/417
- IPC分类号: G11C11/417 ; G09G5/36 ; G09G5/39 ; G09G5/393 ; G11C7/06 ; G11C11/407 ; G11C11/409 ; G11C11/414 ; H03K19/013 ; H03K19/0944 ; G11C7/00 ; H03K19/086
摘要:
A high-speed memory employing the pipeline technique is disclosed, in which the minimum operating cycle time is reduced by use of a latch circuit for a small signal using a bipolar transistor. A small-signal latch circuit operating at a signal smaller than an output signal level is inserted between an amplifier circuit for amplifying the data held in a memory cell circuit and an output buffer circuit. A switch signal is also interposed between the latch circuit and the amplifier circuit, thereby shortening the cycle time.
公开/授权文献
信息查询
IPC分类: