发明授权
US5440509A Electrically erasable programmable read-only memory with NAND cell
structure and intermediate level voltages initially applied to bit lines
失效
电可擦除可编程只读存储器,NAND单元结构和中间电平电压最初应用于位线
- 专利标题: Electrically erasable programmable read-only memory with NAND cell structure and intermediate level voltages initially applied to bit lines
- 专利标题(中): 电可擦除可编程只读存储器,NAND单元结构和中间电平电压最初应用于位线
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申请号: US22392申请日: 1993-02-24
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公开(公告)号: US5440509A公开(公告)日: 1995-08-08
- 发明人: Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
- 申请人: Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX62-290858 19871118; JPX63-111620 19880510; JPX63-204670 19880819
- 主分类号: G11C17/00
- IPC分类号: G11C17/00 ; G11C16/02 ; G11C16/04 ; G11C16/06 ; G11C16/08 ; G11C16/30 ; H01L27/115
摘要:
An erasable programmable read-only memory (EPROM) with a NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected in series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" level voltage (approximately 0 V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.
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