公开(公告)号：US5050125A

公开(公告)日：1991-09-17

申请号：US272404

申请日：1988-11-17

申请人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30

摘要： An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" Level voltage (approximately O V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.

摘要翻译： 具有包括NAND单元块的NAND单元结构的可擦除可编程只读存储器，每个NAND单元块具有连接到相应位线的选择晶体管和连接的存储单元晶体管。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。 提供控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约为0V），对位于所选择的单元之间的字线或字线施加“H”电平电压（大约20V） 字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入特定位线的数据相对应的电压，以及将“H”和“L”电平电压之间的中间电压施加到 未选择的位线，从而通过隧道将数据写入所选择的单元。 如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

公开(公告)号：US5440509A

公开(公告)日：1995-08-08

申请号：US22392

申请日：1993-02-24

申请人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115

摘要： An erasable programmable read-only memory (EPROM) with a NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected in series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" level voltage (approximately 0 V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.

摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器（EPROM）包括NAND单元块，每个单元块具有连接到相应位线的选择晶体管和串联连接的存储单元晶体管。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。 提供一种控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约0V），对位于第一个单元之间的字线或字线施加“H”电平电压（大约20V） 选择字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入到特定位线的数据相对应的电压，以及在“H”和“L”电平电压之间施加中间电压 到未选择的位线，从而通过隧道将数据写入所选择的单元。 如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

公开(公告)号：US5508957A

公开(公告)日：1996-04-16

申请号：US312072

申请日：1994-09-26

申请人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/115 ,  G11C16/06 ,  H01L29/788

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115

摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管 晶体管和地。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。 在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压 将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元 。 用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

公开(公告)号：US5400279A

公开(公告)日：1995-03-21

申请号：US67005

申请日：1993-05-26

申请人： Masaki Momodomi ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba

发明人： Masaki Momodomi ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C7/00

CPC分类号： G11C16/32 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

摘要： An electrically erasable programmable read-only memory has an array of programmable memory cells connected to parallel bit lines on a semiconductive substrate. The memory cells include NAND cell blocks each of which has a first selection transistor coupled to a corresponding bit line, a second selection transistor coupled to the ground potential, and a series array of memory cell transistors each having a floating gate and a control gate. Word lines are respectively connected to the control gates of the memory cell transistors. In a data read mode, a selection transistor of a certain NAND cell block including a selected memory cell transistor is rendered conductive to connect this cell block to a bit line associated therewith. Under such a condition, a low or "L" level voltage is applied by a row decoder & bootstrap circuit section to a word line connected to the selected memory cell transistor, and a pulse voltage signal having a high or "H" level is supplied by the row decoder & bootstrap circuit section to the remaining word lines, so that data stored in the selected memory cell is read out. The "H" level of the voltage signal is higher than the power supply voltage and yet lower than a normal "H" level used in data write and erase modes. The pulse width of the pulse voltage signal is shorter than the period of one read cycle.

摘要翻译： 电可擦除可编程只读存储器具有连接到半导体衬底上的并行位线的可编程存储器单元阵列。 存储器单元包括NAND单元块，每个NAND单元块具有耦合到对应位线的第一选择晶体管，耦合到地电位的第二选择晶体管，以及每个具有浮置栅极和控制栅极的存储单元晶体管的串联阵列。 字线分别连接到存储单元晶体管的控制栅极。 在数据读取模式中，将包括所选存储单元晶体管的某个NAND单元块的选择晶体管导通，以将该单元块连接到与其相关联的位线。 在这种情况下，由行解码器和自举电路部分将低电平或“L”电平施加到连接到所选择的存储单元晶体管的字线，并且提供具有高或“H”电平的脉冲电压信号 通过行解码器和引导电路部分到剩余的字线，使得读出存储在所选存储单元中的数据。 电压信号的“H”电平高于电源电压，但低于在数据写入和擦除模式下使用的正常“H”电平。 脉冲电压信号的脉冲宽度比一个读周期的周期短。

公开(公告)号：US20080217617A1

公开(公告)日：2008-09-11

申请号：US11988388

申请日：2006-07-05

申请人： Shigetoshi Sugawa ,  Akihiro Morimoto ,  Makoto Fujimura ,  Takeyoshi Katoh ,  Masahiko Chiba ,  Tomoyo Hirayama

发明人： Shigetoshi Sugawa ,  Akihiro Morimoto ,  Makoto Fujimura ,  Takeyoshi Katoh ,  Masahiko Chiba ,  Tomoyo Hirayama

IPC分类号： H01L29/04 ,  H05K1/03 ,  H01L21/336 ,  H05K3/00

CPC分类号： H01L29/78636 ,  G02F1/1368 ,  H01L27/124 ,  H01L27/1244 ,  H01L29/4908 ,  H01L29/78603 ,  Y10T29/49155

摘要： A gate electrode or a gate wiring of a thin-film transistor has a four-layer structure including an adhesive base layer, a catalyst layer, a wiring metal layer, and a wiring metal anti-diffusion layer which are laminated in this order. With this structure, adhesion and flatness are improved. In this case, the adhesive base layer is formed by a resin having a structure capable of coordinating to a metal. Hence, adhesion with an insulating substrate can be improved. Further, the wiring metal anti-diffusion layer is formed on the wiring metal layer, so that diffusion of a wiring metal can be inhibited. Thus, characteristics of the thin-film transistor can be improved.

摘要翻译： 薄膜晶体管的栅电极或栅极布线具有依次层叠的包括粘合剂基层，催化剂层，布线金属层和布线金属防扩散层的四层结构。 利用这种结构，提高了粘合性和平坦度。 在这种情况下，粘合剂基层由具有能够与金属配位的结构的树脂形成。 因此，可以提高与绝缘基板的粘合性。 此外，布线金属反扩散层形成在布线金属层上，从而可以抑制布线金属的扩散。 因此，可以提高薄膜晶体管的特性。

公开(公告)号：US5030833A

公开(公告)日：1991-07-09

申请号：US254655

申请日：1988-09-28

申请人： Yoshiki Nozaka ,  Tetsuro Katsuta ,  Masahiko Chiba ,  Hiroshi Miyama

发明人： Yoshiki Nozaka ,  Tetsuro Katsuta ,  Masahiko Chiba ,  Hiroshi Miyama

IPC分类号： B31B1/74 ,  B65H7/02 ,  D21H21/16 ,  D21H21/30 ,  D21H23/78 ,  G01N21/64

CPC分类号： G01N21/64 ,  B31B1/00 ,  B65H7/02 ,  D21H23/78 ,  B31B2201/95 ,  B65H2511/10 ,  B65H2511/512 ,  B65H2513/51 ,  B65H2515/60 ,  D21H21/16 ,  D21H21/30 ,  G01N2021/8663

摘要： An ultraviolet beam from an ultraviolet radiation source is projected to an object having a fluorescent substance such as an adhesive-applied position on a continuous sheet of paper which is being transported and the luminous emission from the fluorescent substance is detected by light reception elements in a detection unit. In this case, at least more than two light reception elements are provided and the arithmetic process of the value of the output from each of the light reception elements is executed by a control computer disposed in a device main body. The value thus obtained is compared with a comparison value stored in storage means, thereby detecting the failure or the degree of adhesive application. When the failure of adhesive application is detected, an alarm buzzer is actuated while a lamp is turned on.The invention is therefore utilized for the inspection of portions to which an adhesive is applied in the adhesive application step carried out by collators, box-making machines, book-binding machines or the like.

摘要翻译： PCT No.PCT / JP88 / 00109 Sec。 371日期：1988年9月28日 102（e）日期1988年9月28日PCT提交1988年2月5日PCT公布。 出版物WO88 / 05909 日期：1988年8月11日。紫外线辐射源的紫外线束被投射到被输送的连续纸上具有诸如粘合剂施加位置之类的荧光物质的物体，并且来自荧光物质的发光是 由检测单元中的光接收元件检测。 在这种情况下，设置至少两个以上的光接收元件，并且通过设置在设备主体中的控制计算机执行来自每个光接收元件的输出值的运算处理。 将如此获得的值与存储装置中存储的比较值进行比较，从而检测故障或粘合剂的使用程度。 当检测到粘合剂应用的故障时，在灯亮起的同时启动报警蜂鸣器。 因此，本发明用于在由整理机，制盒机，装订机等进行的粘合剂施加步骤中检查施加粘合剂的部分。