利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

83 条记录 (耗时 0.035 秒)

    Electrically erasable programmable read-only memory with NAND cellstructure
    1.
    发明授权
    Electrically erasable programmable read-only memory with NAND cellstructure 失效
    具有NAND单元结构的电可擦除可编程只读存储器

    公开(公告)号：US5050125A

    公开(公告)日：1991-09-17

    申请号：US272404

    申请日：1988-11-17

    申请人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

    发明人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

    IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30

    摘要： An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" Level voltage (approximately O V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.

    摘要翻译： 具有包括NAND单元块的NAND单元结构的可擦除可编程只读存储器，每个NAND单元块具有连接到相应位线的选择晶体管和连接的存储单元晶体管。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。 提供控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约为0V），对位于所选择的单元之间的字线或字线施加“H”电平电压（大约20V） 字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入特定位线的数据相对应的电压，以及将“H”和“L”电平电压之间的中间电压施加到 未选择的位线，从而通过隧道将数据写入所选择的单元。 如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

    Electrically erasable programmable read-only memory with NAND cell structure and intermediate level voltages initially applied to bit lines
    2.
    发明授权
    Electrically erasable programmable read-only memory with NAND cell structure and intermediate level voltages initially applied to bit lines 失效
    电可擦除可编程只读存储器，NAND单元结构和中间电平电压最初应用于位线

    公开(公告)号：US5440509A

    公开(公告)日：1995-08-08

    申请号：US22392

    申请日：1993-02-24

    申请人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

    发明人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115

    CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115

    摘要： An erasable programmable read-only memory (EPROM) with a NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected in series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" level voltage (approximately 0 V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.

    摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器（EPROM）包括NAND单元块，每个单元块具有连接到相应位线的选择晶体管和串联连接的存储单元晶体管。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。 提供一种控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约0V），对位于第一个单元之间的字线或字线施加“H”电平电压（大约20V） 选择字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入到特定位线的数据相对应的电压，以及在“H”和“L”电平电压之间施加中间电压 到未选择的位线，从而通过隧道将数据写入所选择的单元。 如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

    Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through
    3.
    发明授权
    Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through 失效
    具有NAND单元结构的非易失性半导体存储器和具有不同通道长度的开关晶体管以减少穿通

    公开(公告)号：US5508957A

    公开(公告)日：1996-04-16

    申请号：US312072

    申请日：1994-09-26

    申请人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

    发明人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

    IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/115 ,  G11C16/06 ,  H01L29/788

    CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115

    摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

    摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管 晶体管和地。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。 在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压 将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元 。 用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

    Non-volatile semiconductor memory device with nand type memory cell arrays
    5.
    发明授权
    Non-volatile semiconductor memory device with nand type memory cell arrays 失效
    具有n型存储单元阵列的非易失性半导体存储器件

    公开(公告)号：US5978265A

    公开(公告)日：1999-11-02

    申请号：US746176

    申请日：1991-08-15

    申请人： Ryouhei Kirisawa ,  Riichiro Shirota ,  Ryozo Nakayama ,  Seiichi Aritome ,  Masaki Momodomi ,  Yasuo Itoh ,  Fujio Masuoka

    发明人： Ryouhei Kirisawa ,  Riichiro Shirota ,  Ryozo Nakayama ,  Seiichi Aritome ,  Masaki Momodomi ,  Yasuo Itoh ,  Fujio Masuoka

    IPC分类号： G11C17/12 ,  G11C16/04 ,  G11C16/10 ,  G11C17/00 ,  G11C11/34

    CPC分类号： G11C16/0483 ,  G11C16/10

    摘要： An electrically erasable programmable read-only memory is disclosed which has programmable memory cells connected to parallel bit lines provided above a semiconductor substrate. The memory cells include NAND cell blocks each of which has a series array of memory cell transistors. Parallel word lines are connected to the control gates of the memory cell transistors, respectively. In a data write mode, a selection transistor in a certain NAND cell block including a selected memory cell is rendered conductive to connect the certain cell block to a corresponding bit line associated therewith. Under such a condition, electrons are tunnel-injected into a floating gate of the selected memory cell transistor, and the threshold value of the certain transistor is increased to be a positive value. A logical data is thus written in the selected memory cell transistor. The data in the selected cell transistor is erased by discharging carriers accumulated in the floating gate thereof to its drain or the substrate, so that the threshold value of the certain transistor is decreased to be a negative value.

    摘要翻译： 公开了一种电可擦除可编程只读存储器，其具有连接到设置在半导体衬底上的并行位线的可编程存储器单元。 存储单元包括NAND单元块，每个NAND单元具有存储单元晶体管的串联阵列。 并行字线分别连接到存储单元晶体管的控制栅极。 在数据写入模式中，包括所选择的存储单元的某个NAND单元块中的选择晶体管被导通以将特定单元块连接到与其相关联的相应位线。 在这种条件下，电子被隧道注入到所选择的存储单元晶体管的浮动栅极中，并且特定晶体管的阈值增加到正值。 因此，逻辑数据被写入所选择的存储单元晶体管中。 通过将其浮置栅极中累积的载流子放电到其漏极或衬底来擦除所选择的单元晶体管中的数据，使得某个晶体管的阈值降低为负值。

    Electrically erasable programmable read-only memory with NAND cell structure
    6.
    再颁专利
    Electrically erasable programmable read-only memory with NAND cell structure 失效
    具有NAND单元结构的电可擦除可编程只读存储器

    公开(公告)号：USRE35838E

    公开(公告)日：1998-07-07

    申请号：US430271

    申请日：1995-04-28

    申请人： Masaki Momodomi ,  Fujio Masuoka ,  Riichiro Shirota ,  Yasuo Itoh ,  Kazunori Ohuchi ,  Ryouhei Kirisawa

    发明人： Masaki Momodomi ,  Fujio Masuoka ,  Riichiro Shirota ,  Yasuo Itoh ,  Kazunori Ohuchi ,  Ryouhei Kirisawa

    IPC分类号： G11C16/16 ,  G11C17/00

    CPC分类号： G11C16/16

    摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.

    摘要翻译： 公开了具有NAND单元结构的可擦除可编程只读存储器，其具有设置在N型衬底上的存储单元。 存储器单元被分成NAND单元块，每个单元块具有存储单元晶体管的串联阵列。 每个晶体管具有浮置栅极，连接到字线的控制栅极和用作其源极和漏极的N型扩散层。 这些半导体层形成在形成于基板的表面区域的P型阱层中。 阱层用作表面击穿防止层。 在数据擦除模式期间，存储在所有存储单元中的数据同时被擦除。 在擦除模式之后的数据写入模式期间，当选择某个NAND单元块时，NAND单元块中的存储单元依次进行数据写入。 当数据被写入所选择的NAND单元块中的某个存储单元中时，该特定存储单元的控制栅极被提供有如此高的电压，以形成强电场，以允许在浮置栅极 的存储单元和阱层。 因此，只能选择所选单元格。

    Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation
    8.
    发明授权
    Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation 失效
    具有NAND单元结构的电可擦除可编程只读存储器，可抑制存储单元阈值电压变化

    公开(公告)号：US4939690A

    公开(公告)日：1990-07-03

    申请号：US290427

    申请日：1988-12-27

    申请人： Masaki Momodomi ,  Riichiro Shirota ,  Yasuo Itoh ,  Satoshi Inoue ,  Fujio Masuoka ,  Ryozo Nakayama ,  Ryouhei Kirisawa

    发明人： Masaki Momodomi ,  Riichiro Shirota ,  Yasuo Itoh ,  Satoshi Inoue ,  Fujio Masuoka ,  Ryozo Nakayama ,  Ryouhei Kirisawa

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483

    摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which includes NAND cell blocks each of which has a selection transistor connected to a corresponding bit line and a series array of memory cell transistors. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data erase mode all the memory cells are simultaneously erased by applying a "H" level potential to the control gates of the memory cells and a "L" level potential to the bit lines. Prior to such a simultaneous erase, charges are removed from charge accumulation layers of the memory cells so that the threshold values of the memory cells are initialized. The threshold initialization is performed on the series-arrayed memory cell transistors in the NAND cell block in sequence.

    摘要翻译： 公开了具有NAND单元结构的可擦除可编程只读存储器，其包括NAND单元块，每个NAND单元具有连接到相应位线的选择晶体管和存储单元晶体管的串联阵列。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据擦除模式下，通过向存储单元的控制栅极施加“H”电平电位，并将位线的“L”电平电位同时擦除所有存储单元。 在这种同时擦除之前，从存储器单元的电荷累积层去除电荷，使得存储单元的阈值被初始化。 对NAND单元块中的串联存储单元晶体管依次执行阈值初始化。

    Nonvolatile semiconductor memory device with NAND cell structure
    9.
    发明授权
    Nonvolatile semiconductor memory device with NAND cell structure 失效
    具有NAND单元结构的非易失性半导体存储器件

    公开(公告)号：US5400279A

    公开(公告)日：1995-03-21

    申请号：US67005

    申请日：1993-05-26

    申请人： Masaki Momodomi ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba

    发明人： Masaki Momodomi ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C7/00

    CPC分类号： G11C16/32 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

    摘要： An electrically erasable programmable read-only memory has an array of programmable memory cells connected to parallel bit lines on a semiconductive substrate. The memory cells include NAND cell blocks each of which has a first selection transistor coupled to a corresponding bit line, a second selection transistor coupled to the ground potential, and a series array of memory cell transistors each having a floating gate and a control gate. Word lines are respectively connected to the control gates of the memory cell transistors. In a data read mode, a selection transistor of a certain NAND cell block including a selected memory cell transistor is rendered conductive to connect this cell block to a bit line associated therewith. Under such a condition, a low or "L" level voltage is applied by a row decoder & bootstrap circuit section to a word line connected to the selected memory cell transistor, and a pulse voltage signal having a high or "H" level is supplied by the row decoder & bootstrap circuit section to the remaining word lines, so that data stored in the selected memory cell is read out. The "H" level of the voltage signal is higher than the power supply voltage and yet lower than a normal "H" level used in data write and erase modes. The pulse width of the pulse voltage signal is shorter than the period of one read cycle.

    摘要翻译： 电可擦除可编程只读存储器具有连接到半导体衬底上的并行位线的可编程存储器单元阵列。 存储器单元包括NAND单元块，每个NAND单元块具有耦合到对应位线的第一选择晶体管，耦合到地电位的第二选择晶体管，以及每个具有浮置栅极和控制栅极的存储单元晶体管的串联阵列。 字线分别连接到存储单元晶体管的控制栅极。 在数据读取模式中，将包括所选存储单元晶体管的某个NAND单元块的选择晶体管导通，以将该单元块连接到与其相关联的位线。 在这种情况下，由行解码器和自举电路部分将低电平或“L”电平施加到连接到所选择的存储单元晶体管的字线，并且提供具有高或“H”电平的脉冲电压信号 通过行解码器和引导电路部分到剩余的字线，使得读出存储在所选存储单元中的数据。 电压信号的“H”电平高于电源电压，但低于在数据写入和擦除模式下使用的正常“H”电平。 脉冲电压信号的脉冲宽度比一个读周期的周期短。