发明授权
US5561772A Expansion bus system for replicating an internal bus as an external bus
with logical interrupts replacing physical interrupt lines
失效
扩展总线系统,用于复制内部总线作为外部总线,逻辑中断替代物理中断线
- 专利标题: Expansion bus system for replicating an internal bus as an external bus with logical interrupts replacing physical interrupt lines
- 专利标题(中): 扩展总线系统,用于复制内部总线作为外部总线,逻辑中断替代物理中断线
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申请号: US280924申请日: 1994-07-26
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公开(公告)号: US5561772A公开(公告)日: 1996-10-01
- 发明人: Pascal Dornier , Dan Kikinis , William J. Seiler , William S. Jacobs
- 申请人: Pascal Dornier , Dan Kikinis , William J. Seiler , William S. Jacobs
- 申请人地址: CA San Mateo
- 专利权人: Elonex Technologies, Inc.
- 当前专利权人: Elonex Technologies, Inc.
- 当前专利权人地址: CA San Mateo
- 主分类号: F02B75/02
- IPC分类号: F02B75/02 ; G06F13/38 ; G06F13/42 ; G06K15/00 ; H04M1/725 ; H04M3/42 ; H04N1/00 ; H04N1/04 ; H04N1/113 ; H04N1/12 ; G06F9/46 ; G06F13/24 ; G06F13/364
摘要:
A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to "high" memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM, allowing various models and types of CPUs to be supported. In this aspect, supported CPUs are interchangeable in the system. In another aspect a default interface attaches to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.
公开/授权文献
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