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    Peripheral device control through integrated drive electronics
    1.
    发明授权
    Peripheral device control through integrated drive electronics 失效
    通过集成驱动电子设备进行外围设备控制

    公开(公告)号：US5964848A

    公开(公告)日：1999-10-12

    申请号：US90509

    申请日：1998-06-04

    Applicant: Dan Kikinis ,  Pascal Dornier

    Inventor： Dan Kikinis ,  Pascal Dornier

    IPC: G06F3/06 ,  G06F13/42 ,  G06F15/04

    CPC classification number: G06F3/0601 ,  G06F13/4226 ,  G06F3/0607 ,  G06F3/0661 ,  G06F3/0674 ,  G06F3/0682 ,  G06F2003/0692

    Abstract: An IDE interface communicates with peripheral devices not conforming to ST506 specification by providing firmware to microcontrollers mounted on the non-conforming peripheral devices to translate between the data structure of an ST506 specification device and the data structure of the non-conforming device. CD-ROM and cartridge tape drive communication is provided. An enhanced IDE interface communicates with multiple peripheral devices by adding a selective ability to the firmware of the conventional IDE interface.

    Abstract translation: IDE接口与不符合ST506规范的外围设备通信，将固件提供给安装在不合格外围设备上的微控制器，以便在ST506规范设备的数据结构与不合格设备的数据结构之间进行转换。 提供CD-ROM和盒式磁带驱动器通信。 增强的IDE接口通过向常规IDE接口的固件添加选择性能力与多个外围设备进行通信。

    Structure and method for mapping interrupt requests in a high-speed CPU interconnect bus system
    2.
    发明授权
    Structure and method for mapping interrupt requests in a high-speed CPU interconnect bus system 失效
    在高速CPU互联总线系统中映射中断请求的结构和方法

    公开(公告)号：US5805901A

    公开(公告)日：1998-09-08

    申请号：US753254

    申请日：1996-11-12

    Applicant: Pascal Dornier ,  Dan Kikinis

    Inventor： Pascal Dornier ,  Dan Kikinis

    IPC: F02B75/02 ,  G06F13/24 ,  G06F13/42 ,  G06F13/38

    CPC classification number: G06F13/24 ,  G06F13/423 ,  F02B2075/027 ,  Y02B60/1228 ,  Y02B60/1235

    Abstract: A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to "high" memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM allowing various models and types of CPUs to be supported. Supported CPUs are interchangeable in the system. In another aspect a default interface attached to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.

    Abstract translation: 用于通用计算机的压缩I / O总线系统在42个专用并行信号路径中的32个多路复用32位数据和地址，并且通过将由外围设备产生的总线请求映射到系统RAM的“高”存储器部分来优化总线结构 不致力于其他目的。 在一个方面，总线控制器是可编程的，以选择存储在系统RAM中的转换程序，允许支持各种型号和类型的CPU。 支持的CPU在系统中是可互换的。 在另一方面，附加到本发明的压缩I / O总线的默认接口，并且将优化的压缩总线和ISA总线或EISA总线之一之间的总线状态转换。

    Timer-controlled computer system power management
    4.
    发明授权
    Timer-controlled computer system power management 失效
    定时控制计算机系统电源管理

    公开(公告)号：US5721936A

    公开(公告)日：1998-02-24

    申请号：US687162

    申请日：1996-07-24

    Applicant: Dan Kikinis ,  Pascal Dornier

    Inventor： Dan Kikinis ,  Pascal Dornier

    IPC: G06F1/26 ,  G06F1/00 ,  G06F1/32 ,  G06F1/14

    CPC classification number: G06F1/3215 ,  G06F1/32 ,  G06F1/3203

    Abstract: A system for managing power levels for a general purpose computer having a standby and a full-power mode of operation provides apparatus and a method for monitoring times of user input and control routines for using the times of user input to calculate optimum times for initiating full power operation and standby mode. The control routines are configured to provide the optimum times to a real time clock that remains powered in the standby mode, which triggers switching elements to initiate full power and standby mode. In one embodiment of the system, startup and standby may be initiated either by user input or automatically by the power management system. Startup and standby initiation times may be different for different days and time periods based on both preprogrammed and calculated values.

    Abstract translation: 用于管理具有备用和全功率操作模式的通用计算机的功率水平的系统提供用于监视用户输入和控制例程的时间的装置和方法，以用于使用用户输入的时间来计算用于启动完全的最佳时间 电源运行和待机模式。 控制例程被配置为向待机模式下保持供电的实时时钟提供最佳时间，这触发开关元件启动全功率和待机模式。 在系统的一个实施例中，可以通过用户输入或由电力管理系统自动启动启动和备用。 基于预编程和计算值的不同日期和时间段的启动和待机启动时间可能不同。

    Interactive system for calibration of display monitors
    9.
    发明授权
    Interactive system for calibration of display monitors 失效
    用于校准显示器的交互式系统

    公开(公告)号：US5565897A

    公开(公告)日：1996-10-15

    申请号：US307529

    申请日：1994-09-16

    Applicant: Dan Kikinis ,  Pascal Dornier

    Inventor： Dan Kikinis ,  Pascal Dornier

    IPC: G06F3/153 ,  G06F3/023 ,  G06F3/048 ,  G09G1/16 ,  G09G5/00 ,  G09G5/08 ,  G09G5/18 ,  H04N17/04 ,  G09G1/04

    CPC classification number: G09G1/165 ,  G06F3/04897 ,  H04N17/04 ,  G09G2320/0606 ,  G09G2320/0626 ,  G09G2320/066 ,  G09G2320/0693 ,  G09G2320/08 ,  G09G2330/021 ,  G09G2370/04 ,  G09G5/006 ,  Y10S345/904

    Abstract: A system for adjusting signals to a CRT in a video monitor utilizes an interactive display having shapes that appear rectangular on a properly adjusted monitor and dragging handles associated with the shapes. Control routines executed on a host computer associate pointer position and movement in dragging the handles with creation of signals to be sent to the monitor to correct signals to the CRT to produce a properly sized, positioned, and shaped display. In one embodiment, digital values are placed in serial packets on a VSYNC line from the host to the video monitor, and a microcontroller in the monitor receives the digital values and drives circuitry in the monitor according to the received commands and data to adjust the signals to the CRT to correct the display.

    Abstract translation: 用于在视频监视器中调整信号到CRT的系统利用具有在适当调整的监视器上显示为矩形的形状并拖动与形状相关联的手柄的交互式显示器。 在主计算机上执行的控制例程使指针位置和移动在拖动手柄时产生要发送到监视器的信号，以将信号校正到CRT以产生适当尺寸，定位和成形的显示器。 在一个实施例中，将数字值放置在从主机到视频监视器的VSYNC线上的串行分组中，并且监视器中的微控制器根据接收到的命令和数据接收数字值并驱动监视器中的电路，以调整信号 到CRT来纠正显示。

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