发明授权
US5581503A Data line disturbance free memory block divided flash memory and
microcomputer having flash memory therein
失效
数据线无干扰存储器块分割闪存和其中具有闪存的微型计算机
- 专利标题: Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
- 专利标题(中): 数据线无干扰存储器块分割闪存和其中具有闪存的微型计算机
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申请号: US520721申请日: 1995-07-31
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公开(公告)号: US5581503A公开(公告)日: 1996-12-03
- 发明人: Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
- 申请人: Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
- 申请人地址: JPX Tokyo JPX Tokyo
- 专利权人: Hitachi, Ltd.,Hitachi VLSI Engineering Corporation
- 当前专利权人: Hitachi, Ltd.,Hitachi VLSI Engineering Corporation
- 当前专利权人地址: JPX Tokyo JPX Tokyo
- 优先权: JPX4-091919 19920317; JPX4-093908 19920319
- 主分类号: G06F9/445
- IPC分类号: G06F9/445 ; G06F15/78 ; G11C7/10 ; G11C16/04 ; G11C16/10 ; G11C16/16 ; G11C16/26 ; G11C16/30 ; H01L21/8247 ; H01L27/105 ; H01L27/115 ; G11C11/34
摘要:
An electrically rewritable flash memory device which has a memory cell array arranged in rows and columns of memory cells and which is divided into a plurality of memory blocks having different memory capacities. Each memory block having one or more rows of memory cells. A common voltage control circuit is provided for each of the memory blocks for applying a first potential to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation. A microcomputer having a CPU and the above-mentioned electrically rewritable flash memory formed in a single semiconductor chip includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of the CPU and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
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