公开(公告)号：US20140319754A1

公开(公告)日：2014-10-30

申请号：US14255015

申请日：2014-04-17

申请人： Fumiaki TSUCHIYA ,  Kenichi KURODA ,  Yasuhiro TOMITA ,  Maki NISHIDE

发明人： Fumiaki TSUCHIYA ,  Kenichi KURODA ,  Yasuhiro TOMITA ,  Maki NISHIDE

IPC分类号： B65H5/26 ,  B65H7/20

CPC分类号： B65H5/26 ,  B65H7/20 ,  B65H2301/5111 ,  B65H2511/512 ,  G03G15/602

摘要： An automatic document feeder includes a sheet feeding tray on which a document is stacked; a slit glass on which the document is scanned while moving; a discharge path in which the document is conveyed after the document is scanned; a document discharge unit to which the document is discharged through the discharge path; and a stamp device that makes a mark on a scanned surface of the document being in the discharge path. The stamp device includes a printing unit that faces the scanned surface of the document. The printing unit is movable between a first position at which the printing unit faces the document being in the discharge path and a second position at which the printing unit is retracted from the discharge path.

摘要翻译： 自动送纸器包括一个纸张馈送托盘，文档被堆叠在其上; 移动时扫描文件的狭缝玻璃; 在文件被扫描之后文档被传送的排放路径; 原稿排出单元，通过排出路径将文件排出到该文件排出单元; 以及在文档的扫描表面上形成标记的印模装置处于排出路径。 邮票装置包括面向文件扫描表面的打印单元。 打印单元可以在打印单元面对在排出路径中的文档的第一位置和打印单元从排出路径缩回的第二位置之间移动。

公开(公告)号：US08765168B2

公开(公告)日：2014-07-01

申请号：US13505487

申请日：2010-11-08

申请人： Brian H. Clarkson ,  Kenichi Kuroda

发明人： Brian H. Clarkson ,  Kenichi Kuroda

IPC分类号： A61F13/02

CPC分类号： A61K33/42 ,  A61K6/0017 ,  A61K6/0038 ,  A61K6/033 ,  A61K6/083 ,  A61K8/19 ,  A61K8/24 ,  A61K8/8152 ,  A61K9/0063 ,  A61Q11/00 ,  C08L33/00

摘要： Compositions of fluorapatite derivative crystals are disclosed herein. Also disclosed are methods of using these compositions to treat tooth sensitivity, to use as an anticaries treatment, to use as a restorative material, to use as a tooth surface whitener, and to combat or lessen the side effects of tooth whitening.

摘要翻译： 本文公开了氟磷灰石衍生物晶体的组成。 还公开了使用这些组合物来治疗牙齿敏感性，用作防龋处理，用作修复材料，用作牙齿表面增白剂以及抵抗或减轻牙齿美白的副作用的方法。

公开(公告)号：US08426969B2

公开(公告)日：2013-04-23

申请号：US13362385

申请日：2012-01-31

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US20120014723A1

公开(公告)日：2012-01-19

申请号：US13175001

申请日：2011-07-01

申请人： Yoshihisa MIZUMOTO ,  Akihiko KAWATANI ,  Takashi MARUI ,  Kenichi KURODA

发明人： Yoshihisa MIZUMOTO ,  Akihiko KAWATANI ,  Takashi MARUI ,  Kenichi KURODA

IPC分类号： G03G15/08

CPC分类号： G03G15/0818 ,  G03G2215/0634

摘要： The semiconductive roller according to the present invention includes a roller body having an outer peripheral surface made of a crosslinked substance of a semiconductive rubber composition and exhibiting Shore A hardness of not more than 60, the semiconductive rubber composition contains a base polymer made of a mixture of (1) mixed rubber N of liquid nitrile rubber and solid nitrile rubber, (2) chloroprene rubber C, and (3) epichlorohydrin rubber E in a mass ratio (C+E)/N of 10/90 to 80/20, the ratios of the chloroprene rubber and the epichlorohydrin rubber in the total quantity of the base polymer are not less than 5 mass % and not less than 5 mass % respectively, and roller resistance at an applied voltage of 5 V is not less than 104Ω and not more than 109Ω.

摘要翻译： 根据本发明的半导电辊包括：具有由半导体橡胶组合物的交联物质制成的外周表面并且肖氏A硬度不大于60的辊体，所述半导体橡胶组合物含有由混合物制成的基础聚合物 的（1）混合橡胶N为液态丁腈橡胶和固体丁腈橡胶，（2）氯丁二烯橡胶C和（3）表氯醇橡胶E的质量比（C + E）/ N为10/90〜80/20， 氯丁橡胶和表氯醇橡胶在基础聚合物总量中的比例分别不低于5质量％且不小于5质量％，施加电压为5V时的辊电阻不小于104＆OHgr; 不超过109＆OHgr。

公开(公告)号：US20110001209A1

公开(公告)日：2011-01-06

申请号：US12867283

申请日：2009-03-12

申请人： Hiroshi Watanabe ,  Naoki Yutani ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Masayuki Imaizumi ,  Yoshinori Matsuno

发明人： Hiroshi Watanabe ,  Naoki Yutani ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Masayuki Imaizumi ,  Yoshinori Matsuno

IPC分类号： H01L29/47

CPC分类号： H01L29/872 ,  H01L21/0495 ,  H01L24/05 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage. A semiconductor device includes: an n− type semiconductor layer formed on an n+ type semiconductor substrate; a first electrode that is formed on the n− type semiconductor layer and functions as a Schottky electrode; a GR layer that is a first p type semiconductor layer formed on a surface of the n− type semiconductor layer below an end of the first electrode and a perimeter thereof; a JTE layer that is formed of a second p type semiconductor layer formed on a bottom and a lateral surface of a groove arranged in a ring shape around the GR layer apart from the GR layer, in a surface of the n− typesemiconductor layer; an insulating film provided so as to cover the GR layer and the JTE layer; and a second electrode that is an Ohmic electrode formed below a rear surface of the n+ type semiconductor substrate.

摘要翻译： 在提供JTE层的端接结构中，存在于半导体层和绝缘膜之间的界面处的水平或缺陷，或从绝缘膜或外部渗透到半导体界面的少量不定性杂质 通过绝缘膜成为漏电流的源极或击穿点，这会降低击穿电压。 半导体器件包括：形成在n +型半导体衬底上的n型半导体层; 形成在n型半导体层上并用作肖特基电极的第一电极; GR层，其是形成在所述第一电极的端部下方的所述n型半导体层的表面上的第一p型半导体层及其周边; 在所述n型半导体层的表面中形成由形成在所述GR层之外的围绕所述GR层的环状的槽的底部和侧面上形成的第二p型半导体层的JTE层; 设置为覆盖GR层和JTE层的绝缘膜; 以及形成在n +型半导体衬底的后表面下方的欧姆电极的第二电极。

公开(公告)号：US07564072B2

公开(公告)日：2009-07-21

申请号：US11142322

申请日：2005-06-02

申请人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yoshinori Matsuno ,  Kenichi Kuroda ,  Hiroshi Sugimoto

发明人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yoshinori Matsuno ,  Kenichi Kuroda ,  Hiroshi Sugimoto

IPC分类号： H01L29/74

CPC分类号： H01L29/0619 ,  H01L29/1608 ,  H01L29/872 ,  Y10S388/917

摘要： A semiconductor device includes an anode electrode in Schottky contact with an n-type drift layer formed in an SiC substrate and a JTE region formed outside the anode electrode. The JTE region is made up of a first p-type zone formed in an upper portion of the drift layer under an edge of the anode electrode and a second p-type zone formed outside the first p-type zone having a lower surface impurity concentration than the first p-type zone. The second p-type zone is provided 15 μm or more outwardly away from the edge of the anode electrode. The surface impurity concentration of the first p-type zone ranges from 1.8×1013 to 4×1013 cm−2, and that of the second p-type zone ranges from 1×1013 to 2.5×1013 cm−2.

摘要翻译： 半导体器件包括与形成在SiC衬底中的n型漂移层肖特基接触的阳极电极和形成在阳极电极外部的JTE区域。 JTE区域由在阳极电极的边缘的漂移层的上部形成的第一p型区域和形成在具有较低表面杂质浓度的第一p型区域外的第二p型区域构成 比第一个p型区域。 第二个p型区域距离阳极电极的边缘向外提供15个或更多个外部。 第一p型区域的表面杂质浓度范围为1.8×1013〜4×1013cm-2，第二p型区域的表面杂质浓度为1×10 13〜2.5×10 13 cm -2。

公开(公告)号：US20090157953A1

公开(公告)日：2009-06-18

申请号：US12320679

申请日：2009-02-02

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

公开(公告)号：US20090134404A1

公开(公告)日：2009-05-28

申请号：US12066366

申请日：2006-04-24

申请人： Hiroshi Sugimoto ,  Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Noboru Mikami ,  Kenichi Kuroda

发明人： Hiroshi Sugimoto ,  Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Noboru Mikami ,  Kenichi Kuroda

IPC分类号： H01L29/24

CPC分类号： H01L29/8611 ,  H01L21/0445 ,  H01L29/045 ,  H01L29/0684 ,  H01L29/1608 ,  H01L29/6606

摘要： On a major surface of an n-type silicon carbide inclined substrate (2) is formed an n-type voltage-blocking layer (3) made of silicon carbide by means of epitaxial growth. On the n-type voltage-blocking layer (3) is formed a p-type silicon carbide region (4) rectangular when viewed from above. On the surface of the p-type silicon carbide region (4) is formed a p-type contact electrode (5). In the p-type silicon carbide region (4), the periphery of the p-type silicon carbide region (4) that is parallel with a (11-20) plane (14a) of the silicon carbide crystal, which is liable to cause avalanche breakdown, is located on the short side. In this manner, the dielectric strength of a silicon carbide semiconductor device can be improved.

摘要翻译： 在n型碳化硅倾斜衬底（2）的主表面上通过外延生长形成由碳化硅制成的n型压阻层（3）。 在从上方观察时，在n型电压阻挡层（3）上形成矩形的p型碳化硅区域（4）。 在p型碳化硅区域（4）的表面上形成p型接触电极（5）。 在p型碳化硅区域（4）中，与碳化硅晶体的（11-20）面（14a）平行的p型碳化硅区域（4）的周边易于引起 雪崩破裂，位于短边。 以这种方式，可以提高碳化硅半导体器件的介电强度。

公开(公告)号：US20080211056A1

公开(公告)日：2008-09-04

申请号：US11978686

申请日：2007-10-30

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohlko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohlko Yamamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，可以通过放置相对较宽区域的第一虚拟图案DP 1，将虚拟图案放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的区域，并且 在虚拟区域FA中具有相对较小面积的第二虚拟图案DP 2 2 。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当虚拟区域FA中的第一伪图案DP 1占据相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US07166893B2

公开(公告)日：2007-01-23

申请号：US10252101

申请日：2002-09-23

申请人： Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

发明人： Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0922 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/11546 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7835 ,  Y10S438/981

摘要： A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.

摘要翻译： 能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。 可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。